4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * (C) Copyright (c) 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/cpm_8260.h>
39 #if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET)
41 #if (CONFIG_ETHER_INDEX == 1)
42 # define PROFF_ENET PROFF_SCC1
43 # define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
44 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
45 # define CMXSCR_MASK (CMXSCR_SC1 |\
49 #elif (CONFIG_ETHER_INDEX == 2)
50 # define PROFF_ENET PROFF_SCC2
51 # define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
52 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
53 # define CMXSCR_MASK (CMXSCR_SC2 |\
57 #elif (CONFIG_ETHER_INDEX == 3)
58 # define PROFF_ENET PROFF_SCC3
59 # define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
60 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
61 # define CMXSCR_MASK (CMXSCR_SC3 |\
64 #elif (CONFIG_ETHER_INDEX == 4)
65 # define PROFF_ENET PROFF_SCC4
66 # define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
67 # define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
68 # define CMXSCR_MASK (CMXSCR_SC4 |\
75 /* Ethernet Transmit and Receive Buffers */
76 #define DBUF_LENGTH 1520
80 #define TOUT_LOOP 1000000
82 static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
84 static uint rxIdx; /* index of the current RX buffer */
85 static uint txIdx; /* index of the current TX buffer */
88 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
89 * immr->udata_bd address on Dual-Port RAM
90 * Provide for Double Buffering
93 typedef volatile struct CommonBufferDescriptor {
94 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
95 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
101 int eth_send(volatile void *packet, int length)
107 printf("scc: bad packet size: %d\n", length);
111 for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
112 if (i >= TOUT_LOOP) {
113 puts ("scc: tx buffer not ready\n");
118 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
119 rtx->txbd[txIdx].cbd_datlen = length;
120 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
123 for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
124 if (i >= TOUT_LOOP) {
125 puts ("scc: tx error\n");
130 /* return only status bits */
131 result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
144 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
146 break; /* nothing received - leave for() loop */
149 length = rtx->rxbd[rxIdx].cbd_datlen;
151 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
153 printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
157 /* Pass the packet up to the protocol layers. */
158 NetReceive(NetRxPackets[rxIdx], length - 4);
162 /* Give the buffer back to the SCC. */
163 rtx->rxbd[rxIdx].cbd_datlen = 0;
165 /* wrap around buffer index when necessary */
166 if ((rxIdx + 1) >= PKTBUFSRX) {
167 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
172 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
179 /**************************************************************
181 * SCC Ethernet Initialization Routine
183 *************************************************************/
185 int eth_init(bd_t *bis)
188 volatile immap_t *immr = (immap_t *)CFG_IMMR;
189 scc_enet_t *pram_ptr;
195 /* assign static pointer to BD area */
196 dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
197 rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
199 /* 24.21 - (1-3): ioports have been set up already */
201 /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
202 immr->im_cpmux.cmx_uar = 0;
203 immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
207 /* 24.21 (6) write RBASE and TBASE to parameter RAM */
208 pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
209 pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
210 pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);
212 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */
213 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */
215 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */
217 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
218 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
221 /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
222 while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
223 immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
226 CPM_CR_INIT_TRX) | CPM_CR_FLG;
228 /* 24.21 - (8-18): Set up parameter RAM */
229 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
230 pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */
231 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
233 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
235 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
237 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
238 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
240 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
241 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
243 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
244 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
245 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
246 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
248 # define ea bis->bi_enetaddr
249 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
250 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
251 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
254 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
256 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
257 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
258 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
259 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
261 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
262 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
263 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
266 /* 24.21 - (19): Initialize RxBD */
267 for (i = 0; i < PKTBUFSRX; i++)
269 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
270 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
271 rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
274 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
276 /* 24.21 - (20): Initialize TxBD */
277 for (i = 0; i < TX_BUF_CNT; i++)
279 rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD |
282 rtx->txbd[i].cbd_datlen = 0; /* Reset */
283 rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
286 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
288 /* 24.21 - (21): Write 0xffff to SCCE */
289 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);
291 /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
292 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
296 /* 24.21 - (23): we don't use ethernet interrupts */
298 /* 24.21 - (24): Clear GSMR_H to enable normal operations */
299 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;
301 /* 24.21 - (25): Clear GSMR_L to enable normal operations */
302 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI |
305 SCC_GSMRL_MODE_ENET);
307 /* 24.21 - (26): Initialize DSR */
308 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
310 /* 24.21 - (27): Initialize PSMR2
314 * NIB = Begin searching for SFD 22 bits after RENA
315 * FDE = Full Duplex Enable
316 * BRO = Reject broadcast packets
317 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
319 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC |
321 #if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
324 #if defined(CONFIG_SCC_ENET_NO_BROADCAST)
327 #if defined(CONFIG_SCC_ENET_PROMISCOUS)
332 /* 24.21 - (28): Write to GSMR_L to enable SCC */
333 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
342 volatile immap_t *immr = (immap_t *)CFG_IMMR;
343 immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
350 volatile immap_t *immr = (immap_t *)CFG_IMMR;
351 immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |