2 * MPC8260 FCC Fast Ethernet
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MPC8260 FCC Fast Ethernet
30 * Basic ET HW initialization and packet RX/TX routines
32 * This code will not perform the IO port configuration. This should be
33 * done in the iop_conf_t structure specific for the board.
36 * add a PHY driver to do the negotiation
37 * reflect negotiation results in FPSMR
38 * look for ways to configure the board specific stuff elsewhere, eg.
39 * config_xxx.h or the board directory
44 #include <asm/cpm_8260.h>
50 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
51 defined(CONFIG_NET_MULTI)
53 static struct ether_fcc_info_s
57 ulong cpm_cr_enet_sblock;
58 ulong cpm_cr_enet_page;
64 #ifdef CONFIG_ETHER_ON_FCC1
75 #ifdef CONFIG_ETHER_ON_FCC2
86 #ifdef CONFIG_ETHER_ON_FCC3
98 /*---------------------------------------------------------------------*/
100 /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
101 #define PKT_MAXDMA_SIZE 1520
103 /* The FCC stores dest/src/type, data, and checksum for receive packets. */
104 #define PKT_MAXBUF_SIZE 1518
105 #define PKT_MINBUF_SIZE 64
107 /* Maximum input buffer size. Must be a multiple of 32. */
108 #define PKT_MAXBLR_SIZE 1536
110 #define TOUT_LOOP 1000000
114 static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
116 #error "txbuf must be 64-bit aligned"
119 static uint rxIdx; /* index of the current RX buffer */
120 static uint txIdx; /* index of the current TX buffer */
123 * FCC Ethernet Tx and Rx buffer descriptors.
124 * Provide for Double Buffering
125 * Note: PKTBUFSRX is defined in net.h
128 typedef volatile struct rtxbd {
129 cbd_t rxbd[PKTBUFSRX];
130 cbd_t txbd[TX_BUF_CNT];
133 /* Good news: the FCC supports external BDs! */
135 static RTXBD rtx __attribute__ ((aligned(8)));
137 #error "rtx must be 64-bit aligned"
140 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
146 printf("fec: bad packet size: %d\n", length);
150 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
151 if (i >= TOUT_LOOP) {
152 printf("fec: tx buffer not ready\n");
157 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
158 rtx.txbd[txIdx].cbd_datlen = length;
159 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
162 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
163 if (i >= TOUT_LOOP) {
164 printf("fec: tx error\n");
170 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
173 /* return only status bits */
174 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
180 static int fec_recv(struct eth_device* dev)
186 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
188 break; /* nothing received - leave for() loop */
190 length = rtx.rxbd[rxIdx].cbd_datlen;
192 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
193 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
196 /* Pass the packet up to the protocol layers. */
197 NetReceive(NetRxPackets[rxIdx], length - 4);
201 /* Give the buffer back to the FCC. */
202 rtx.rxbd[rxIdx].cbd_datlen = 0;
204 /* wrap around buffer index when necessary */
205 if ((rxIdx + 1) >= PKTBUFSRX) {
206 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
210 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
218 static int fec_init(struct eth_device* dev, bd_t *bis)
220 struct ether_fcc_info_s * info = dev->priv;
222 volatile immap_t *immr = (immap_t *)CFG_IMMR;
223 volatile cpm8260_t *cp = &(immr->im_cpm);
224 fcc_enet_t *pram_ptr;
225 unsigned long mem_addr;
231 /* 28.9 - (1-2): ioports have been set up already */
233 /* 28.9 - (3): connect FCC's tx and rx clocks */
234 immr->im_cpmux.cmx_uar = 0;
235 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
238 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
239 immr->im_fcc[info->ether_index].fcc_gfmr =
240 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
242 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
243 immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
245 /* 28.9 - (6): FDSR: Ethernet Syn */
246 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
248 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
252 /* Setup Receiver Buffer Descriptors */
253 for (i = 0; i < PKTBUFSRX; i++)
255 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
256 rtx.rxbd[i].cbd_datlen = 0;
257 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
259 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
261 /* Setup Ethernet Transmitter Buffer Descriptors */
262 for (i = 0; i < TX_BUF_CNT; i++)
264 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
265 rtx.txbd[i].cbd_datlen = 0;
266 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
268 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
270 /* 28.9 - (7): initialise parameter ram */
271 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
273 /* clear whole structure to make sure all reserved fields are zero */
274 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
277 * common Parameter RAM area
279 * Allocate space in the reserved FCC area of DPRAM for the
280 * internal buffers. No one uses this space (yet), so we
281 * can do this. Later, we will add resource management for
284 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
285 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
286 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
288 * Set maximum bytes per receive buffer.
289 * It must be a multiple of 32.
291 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
292 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
293 CFG_CPMFCR_RAMTYPE) << 24;
294 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
295 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
296 CFG_CPMFCR_RAMTYPE) << 24;
297 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
299 /* protocol-specific area */
300 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
301 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
302 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
303 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
305 * Set Ethernet station address.
307 * This is supplied in the board information structure, so we
308 * copy that into the controller.
309 * So, far we have only been given one Ethernet address. We make
310 * it unique by setting a few bits in the upper byte of the
311 * non-static part of the address.
313 #define ea eth_get_dev()->enetaddr
314 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
315 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
316 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
318 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
319 /* pad pointer. use tiptr since we don't need a specific padding char */
320 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
321 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
322 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
323 pram_ptr->fen_rfthr = 1;
324 pram_ptr->fen_rfcnt = 1;
326 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
327 pram_ptr->fen_genfcc.fcc_rbase);
328 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
329 pram_ptr->fen_genfcc.fcc_tbase);
332 /* 28.9 - (8): clear out events in FCCE */
333 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
335 /* 28.9 - (9): FCCM: mask all events */
336 immr->im_fcc[info->ether_index].fcc_fccm = 0;
338 /* 28.9 - (10-12): we don't use ethernet interrupts */
342 * Let's re-initialize the channel now. We have to do it later
343 * than the manual describes because we have just now finished
344 * the BD initialization.
346 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
347 info->cpm_cr_enet_sblock,
349 CPM_CR_INIT_TRX) | CPM_CR_FLG;
351 __asm__ __volatile__ ("eieio");
352 } while (cp->cp_cpcr & CPM_CR_FLG);
354 /* 28.9 - (14): enable tx/rx in gfmr */
355 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
360 static void fec_halt(struct eth_device* dev)
362 struct ether_fcc_info_s * info = dev->priv;
363 volatile immap_t *immr = (immap_t *)CFG_IMMR;
365 /* write GFMR: disable tx/rx */
366 immr->im_fcc[info->ether_index].fcc_gfmr &=
367 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
370 int fec_initialize(bd_t *bis)
372 struct eth_device* dev;
375 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
377 dev = (struct eth_device*) malloc(sizeof *dev);
378 memset(dev, 0, sizeof *dev);
380 sprintf(dev->name, "FCC%d ETHERNET",
381 ether_fcc_info[i].ether_index + 1);
382 dev->priv = ðer_fcc_info[i];
383 dev->init = fec_init;
384 dev->halt = fec_halt;
385 dev->send = fec_send;
386 dev->recv = fec_recv;
394 #endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */