2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
31 * Wolfgang Denk <wd@denx.de>
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
37 * Marius Groeger <mag@sysgo.de>
39 * added HiP7 (8270/8275/8280) processors support by
40 * Yuli Barcohen <yuli@arabellasw.com>
47 #include <asm/processor.h>
48 #include <asm/cpm_8260.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 volatile immap_t *immap = (immap_t *) CFG_IMMR;
55 ulong clock = gd->cpu_clk;
56 uint pvr = get_pvr ();
74 return -1; /* whoops! not an MPC8260 */
78 immr = immap->im_memctl.memc_immr;
79 if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
80 return -1; /* whoops! someone moved the IMMR */
82 printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
85 * the bottom 16 bits of the immr are the Part Number and Mask Number
86 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
87 * RISC Microcode Revision Number (13-10).
88 * For the 8260, Motorola doesn't include the Microcode Revision
91 m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
92 k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
102 printf ("A.1 1K22A-XC");
105 printf ("B.1 1K23A");
108 printf ("B.2 2K23A-XC");
111 printf ("B.3 3K23A");
114 printf ("C.2 6K23A");
117 printf ("A.0(A) 2K25A");
120 printf ("B.1 4K25A");
123 printf ("C.0 5K25A");
126 printf ("0.0 0K49M");
129 printf ("0.1 1K49M");
132 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
136 printf (") at %s MHz\n", strmhz (buf, clock));
141 /* ------------------------------------------------------------------------- */
142 /* configures a UPM by writing into the UPM RAM array */
143 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
144 /* NOTE: the physical address chosen must not overlap into any other area */
145 /* mapped by the memory controller because bank 11 has the lowest priority */
147 void upmconfig (uint upm, uint * table, uint size)
149 volatile immap_t *immap = (immap_t *) CFG_IMMR;
150 volatile memctl8260_t *memctl = &immap->im_memctl;
151 volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
154 /* first set up bank 11 to reference the correct UPM at a dummy address */
156 memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
162 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
164 memctl->memc_mamr = MxMR_OP_WARR;
169 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
171 memctl->memc_mbmr = MxMR_OP_WARR;
176 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
178 memctl->memc_mcmr = MxMR_OP_WARR;
182 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
188 * at this point, the dummy address is set up to access the selected UPM,
189 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
191 * now we simply load the mdr with each word and poke the dummy address.
192 * the MAD is incremented on each access.
195 for (i = 0; i < size; i++) {
196 memctl->memc_mdr = table[i];
200 /* now kill bank 11 */
201 memctl->memc_br11 = 0;
204 /* ------------------------------------------------------------------------- */
207 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
211 volatile immap_t *immap = (immap_t *) CFG_IMMR;
213 immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
215 /* Interrupts and MMU off */
216 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
218 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
219 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
222 * Trying to execute the next instruction at a non-existing address
223 * should cause a machine check, resulting in reset
225 #ifdef CFG_RESET_ADDRESS
226 addr = CFG_RESET_ADDRESS;
229 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
230 * - sizeof (ulong) is usually a valid address. Better pick an address
231 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
233 addr = CFG_MONITOR_BASE - sizeof (ulong);
235 ((void (*)(void)) addr) ();
240 /* ------------------------------------------------------------------------- */
243 * Get timebase clock frequency (like cpu_clk in Hz)
246 unsigned long get_tbclk (void)
248 DECLARE_GLOBAL_DATA_PTR;
252 tbclk = (gd->bus_clk + 3L) / 4L;
257 /* ------------------------------------------------------------------------- */
259 #if defined(CONFIG_WATCHDOG)
260 void watchdog_reset (void)
262 int re_enable = disable_interrupts ();
264 reset_8260_watchdog ((immap_t *) CFG_IMMR);
266 enable_interrupts ();
268 #endif /* CONFIG_WATCHDOG */
270 /* ------------------------------------------------------------------------- */