2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
31 * Wolfgang Denk <wd@denx.de>
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
37 * Marius Groeger <mag@sysgo.de>
39 * added HiP7 (824x/827x/8280) processors support by
40 * Yuli Barcohen <yuli@arabellasw.com>
48 #include <asm/processor.h>
49 #include <asm/cpm_8260.h>
51 #if defined(CONFIG_OF_LIBFDT)
53 #include <libfdt_env.h>
54 #include <fdt_support.h>
57 DECLARE_GLOBAL_DATA_PTR;
59 #if defined(CONFIG_GET_CPU_STR_F)
60 extern int get_cpu_str_f (char *buf);
65 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
66 ulong clock = gd->cpu_clk;
67 uint pvr = get_pvr ();
87 return -1; /* whoops! not an MPC8260 */
91 immr = immap->im_memctl.memc_immr;
92 if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
93 return -1; /* whoops! someone moved the IMMR */
95 #if defined(CONFIG_GET_CPU_STR_F)
97 printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
99 printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
103 * the bottom 16 bits of the immr are the Part Number and Mask Number
104 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
105 * RISC Microcode Revision Number (13-10).
106 * For the 8260, Motorola doesn't include the Microcode Revision
109 m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
110 k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
120 puts ("A.1 1K22A-XC");
126 puts ("B.2 2K23A-XC");
135 puts ("A.0(A) 2K25A");
165 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
169 printf (") at %s MHz\n", strmhz (buf, clock));
174 /* ------------------------------------------------------------------------- */
175 /* configures a UPM by writing into the UPM RAM array */
176 /* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
177 /* NOTE: the physical address chosen must not overlap into any other area */
178 /* mapped by the memory controller because bank 11 has the lowest priority */
180 void upmconfig (uint upm, uint * table, uint size)
182 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
183 volatile memctl8260_t *memctl = &immap->im_memctl;
184 volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
187 /* first set up bank 11 to reference the correct UPM at a dummy address */
189 memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
195 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
197 memctl->memc_mamr = MxMR_OP_WARR;
202 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
204 memctl->memc_mbmr = MxMR_OP_WARR;
209 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
211 memctl->memc_mcmr = MxMR_OP_WARR;
215 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
221 * at this point, the dummy address is set up to access the selected UPM,
222 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
224 * now we simply load the mdr with each word and poke the dummy address.
225 * the MAD is incremented on each access.
228 for (i = 0; i < size; i++) {
229 memctl->memc_mdr = table[i];
233 /* now kill bank 11 */
234 memctl->memc_br11 = 0;
237 /* ------------------------------------------------------------------------- */
239 #if !defined(CONFIG_HAVE_OWN_RESET)
241 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
245 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
247 immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
249 /* Interrupts and MMU off */
250 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
252 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
253 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
256 * Trying to execute the next instruction at a non-existing address
257 * should cause a machine check, resulting in reset
259 #ifdef CONFIG_SYS_RESET_ADDRESS
260 addr = CONFIG_SYS_RESET_ADDRESS;
263 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
264 * - sizeof (ulong) is usually a valid address. Better pick an address
265 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
267 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
269 ((void (*)(void)) addr) ();
273 #endif /* CONFIG_HAVE_OWN_RESET */
275 /* ------------------------------------------------------------------------- */
278 * Get timebase clock frequency (like cpu_clk in Hz)
281 unsigned long get_tbclk (void)
285 tbclk = (gd->bus_clk + 3L) / 4L;
290 /* ------------------------------------------------------------------------- */
292 #if defined(CONFIG_WATCHDOG)
293 void watchdog_reset (void)
295 int re_enable = disable_interrupts ();
297 reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
299 enable_interrupts ();
301 #endif /* CONFIG_WATCHDOG */
303 /* ------------------------------------------------------------------------- */
304 #if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
305 void ft_cpu_setup (void *blob, bd_t *bd)
307 char * cpu_path = "/cpus/" OF_CPU;
309 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
310 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
311 fdt_fixup_ethernet(blob);
314 do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
315 do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
316 do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
318 #endif /* CONFIG_OF_LIBFDT */
321 * Initializes on-chip ethernet controllers.
322 * to override, implement board_eth_init()
324 int cpu_eth_init(bd_t *bis)
326 #if defined(CONFIG_ETHER_ON_FCC)
329 #if defined(CONFIG_ETHER_ON_SCC)
330 mpc82xx_scc_enet_initialize(bd);