3 /*********************************************************
5 * copyright @ Motorola, 1999
7 *********************************************************/
9 #define I2O_REG_OFFSET 0x0004
11 #define PCI_CFG_CLA 0x0B
12 #define PCI_CFG_SCL 0x0A
13 #define PCI_CFG_PIC 0x09
15 #define I2O_IMR0 0x0050
16 #define I2O_IMR1 0x0054
17 #define I2O_OMR0 0x0058
18 #define I2O_OMR1 0x005C
20 #define I2O_ODBR 0x0060
21 #define I2O_IDBR 0x0068
23 #define I2O_OMISR 0x0030
24 #define I2O_OMIMR 0x0034
25 #define I2O_IMISR 0x0100
26 #define I2O_IMIMR 0x0104
28 /* accessable to PCI master but local processor */
29 #define I2O_IFQPR 0x0040
30 #define I2O_OFQPR 0x0044
32 /* accessable to local processor */
33 #define I2O_IFHPR 0x0120
34 #define I2O_IFTPR 0x0128
35 #define I2O_IPHPR 0x0130
36 #define I2O_IPTPR 0x0138
37 #define I2O_OFHPR 0x0140
38 #define I2O_OFTPR 0x0148
39 #define I2O_OPHPR 0x0150
40 #define I2O_OPTPR 0x0158
41 #define I2O_MUCR 0x0164
42 #define I2O_QBAR 0x0170
46 typedef enum _i2o_status
58 typedef enum _queue_size
67 typedef enum _location
69 LOCAL = 0, /* used by local processor to access its own on board device,
70 local processor's eumbbar is required */
71 REMOTE, /* used by PCI master to access the devices on its PCI device,
72 device's pcsrbar is required */
76 typedef enum _i2o_in_db
79 MC, /* machine check */
82 /* I2O PCI configuration identification */
83 typedef struct _i2o_iop
85 unsigned int base_class : 8;
86 unsigned int sub_class : 8;
87 unsigned int prg_code : 8;
90 /* I2O Outbound Message Interrupt Status Register */
91 typedef struct _i2o_om_stat
93 unsigned int rsvd0 : 26;
94 unsigned int opqi : 1;
95 unsigned int rsvd1 : 1;
97 unsigned int rsvd2 : 1;
98 unsigned int om1i : 1;
99 unsigned int om0i : 1;
102 /* I2O inbound Message Interrupt Status Register */
103 typedef struct _i2o_im_stat
105 unsigned int rsvd0 : 23;
106 unsigned int ofoi : 1;
107 unsigned int ipoi : 1;
108 unsigned int rsvd1 : 1;
109 unsigned int ipqi : 1;
110 unsigned int mci : 1;
111 unsigned int idi : 1;
112 unsigned int rsvd2 : 1;
113 unsigned int im1i : 1;
114 unsigned int im0i : 1;
118 Enable the interrupt associated with in/out bound msg
120 Inbound message interrupt generated by PCI master and serviced by local processor
121 local processor needs to enable its inbound interrupts it wants to handle (LOCAL)
123 Outbound message interrupt generated by local processor and serviced by PCI master
124 PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
126 extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
127 unsigned int base, /* pcsrbar/eumbbar */
128 unsigned char n ); /* b'1' - msg 0
134 Disable the interrupt associated with in/out bound msg
136 local processor needs to disable its inbound interrupts it is not interested (LOCAL)
138 PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
140 extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
141 unsigned int base, /* pcsrbar/eumbbar */
142 unsigned char n ); /* b'1' - msg 0
148 Read the msg register either from local inbound msg 0/1,
149 or an outbound msg 0/1 of devices.
151 If it is not local, pcsrbar must be passed to the function.
152 Otherwise eumbbar is passed.
154 If it is remote, outbound msg of the device is read.
155 Otherwise local inbound msg is read.
157 extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
158 unsigned int base, /*pcsrbar/eumbbar */
159 unsigned int n, /* 0 or 1 */
163 Write to nth Msg register either on local outbound msg 0/1,
164 or aninbound msg 0/1 of devices
166 If it is not local, pcsrbar must be passed to the function.
167 Otherwise eumbbar is passed.
169 If it is remote, inbound msg on the device is written.
170 Otherwise local outbound msg is written.
172 extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
173 unsigned int base, /*pcsrbar/eumbbar */
174 unsigned int n, /* 0 or 1 */
178 Enable the In/Out DoorBell Interrupt
180 InDoorBell interrupt is generated by PCI master and serviced by local processor
181 local processor needs to enable its inbound doorbell interrupts it wants to handle
183 OutDoorbell interrupt is generated by local processor and serviced by PCI master
184 PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
186 extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
187 unsigned int base, /* pcsrbar/eumbbar */
188 unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
191 Disable the In/Out DoorBell Interrupt
193 local processor needs to disable its inbound doorbell interrupts it is not interested
195 PCI master needs to disable outbound doorbell interrupts of devices it is not interested
198 extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
199 unsigned int base, /* pcsrbar/eumbbar */
200 unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
203 Read a local indoorbell register, or an outdoorbell of devices.
204 Reading a doorbell register, the register will be cleared.
206 If it is not local, pcsrbar must be passed to the function.
207 Otherwise eumbbar is passed.
209 If it is remote, outdoorbell register on the device is read.
210 Otherwise local in doorbell is read
212 extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
213 unsigned int base); /* pcsrbar/eumbbar */
216 Write to a local outdoorbell register, or an indoorbell register of devices.
218 If it is not local, pcsrbar must be passed to the function.
219 Otherwise eumbbar is passed.
221 If it is remote, in doorbell register on the device is written.
222 Otherwise local out doorbell is written
224 extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
225 unsigned int base, /* pcsrbar/eumbbar */
226 unsigned int msg ); /* in / out */
229 Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
230 the register will be cleared.
232 The outbound interrupt status is AND with the outbound
233 interrupt mask. The result is returned.
235 PCI master must pass the pcsrbar to the function.
237 extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );
240 Read the inbound msg unit interrupt status. Reading an interrupt status register,
241 the register will be cleared.
243 The inbound interrupt status is AND with the inbound
244 interrupt mask. The result is returned.
246 Local process must pass its eumbbar to the function.
248 extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
251 Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
254 extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
256 unsigned int qba);/* queue base address that must be aligned at 1M */
258 Enable the circular queue
260 extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );
263 Disable the circular queue
265 extern void I2OFIFODisable( unsigned int eumbbar );
268 Enable the circular queue interrupt
269 PCI master enables outbound FIFO interrupt of device
270 Device enables its inbound FIFO interrupt
272 extern void I2OFIFOIntEnable( LOCATION, unsigned int base );
275 Disable the circular queue interrupt
276 PCI master disables outbound FIFO interrupt of device
277 Device disables its inbound FIFO interrupt
279 extern void I2OFIFOIntDisable( LOCATION, unsigned int base );
282 Enable the circular queue overflow interrupt
284 extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );
287 Disable the circular queue overflow interrupt
289 extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
292 Allocate a free msg frame from free FIFO.
294 PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
295 while local processor allocates a free msg frame from outbound free queue(OFTPR)
297 Unless both free queues are initialized, allocating a free MF will return 0xffffffff
299 extern I2OSTATUS I2OFIFOAlloc( LOCATION,
303 Free a used msg frame back to free queue
304 PCI Master frees a MFA through outbound queue port of device(OFQPR)
305 while local processor frees a MFA into its inbound free queue(IFHPR)
307 Used msg frame does not need to be recycled in the order they
310 This function has to be called by PCI master to initialize Inbound free queue
311 and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
313 extern I2OSTATUS I2OFIFOFree( LOCATION,
319 PCI Master posts a msg through inbound queue port of device(IFQPR)
320 while local processor post a msg into its outbound post queue(OPHPR)
322 The total number of msg must be less than the max size of the queue
323 Otherwise queue overflow interrupt will assert.
325 extern I2OSTATUS I2OFIFOPost( LOCATION,
331 PCI Master reads a msg through outbound queue port of device(OFQPR)
332 while local processor reads a msg from its inbound post queue(IPTPR)
334 extern I2OSTATUS I2OFIFOGet( LOCATION,
339 Get the I2O PCI configuration identification register
341 extern I2OSTATUS I2OPCIConfigGet( LOCATION,