2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8220 CPUs
32 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
34 #include <ppc_asm.tmpl>
37 #include <asm/cache.h>
40 #ifndef CONFIG_IDENT_STRING
41 #define CONFIG_IDENT_STRING ""
44 /* We don't want the MMU yet.
47 /* Floating Point enable, Machine Check and Recoverable Interr. */
49 #define MSR_KERNEL (MSR_FP|MSR_RI)
51 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
55 * Set up GOT: Global Offset Table
57 * Use r14 to access the GOT
60 GOT_ENTRY(_GOT2_TABLE_)
61 GOT_ENTRY(_FIXUP_TABLE_)
64 GOT_ENTRY(_start_of_vectors)
65 GOT_ENTRY(_end_of_vectors)
66 GOT_ENTRY(transfer_to_handler)
70 GOT_ENTRY(__bss_start)
80 .ascii " (", __DATE__, " - ", __TIME__, ")"
81 .ascii CONFIG_IDENT_STRING, "\0"
90 li r21, BOOTFLAG_COLD /* Normal Power-On */
94 . = EXC_OFF_SYS_RESET + 0x10
98 li r21, BOOTFLAG_WARM /* Software reboot */
103 mfmsr r5 /* save msr contents */
105 /* replace default MBAR base address from 0x80000000
108 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
110 ori r3, r3, CFG_MBAR@l
112 /* MBAR is mirrored into the MBAR SPR */
115 lis r4, CFG_DEFAULT_MBAR@h
117 #endif /* CFG_DEFAULT_MBAR */
119 /* Initialise the MPC8220 processor core */
120 /*--------------------------------------------------------------*/
124 /* initialize some things that are hard to access from C */
125 /*--------------------------------------------------------------*/
127 /* set up stack in on-chip SRAM */
128 lis r3, CFG_INIT_RAM_ADDR@h
129 ori r3, r3, CFG_INIT_RAM_ADDR@l
130 ori r1, r3, CFG_INIT_SP_OFFSET
132 li r0, 0 /* Make room for stack frame header and */
133 stwu r0, -4(r1) /* clear final stack frame so that */
134 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
136 /* let the C-code set up the rest */
138 /* Be careful to keep code relocatable ! */
139 /*--------------------------------------------------------------*/
141 GET_GOT /* initialize GOT access */
144 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
148 bl board_init_f /* run 1st part of board init code (in Flash)*/
154 .globl _start_of_vectors
158 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
160 /* Data Storage exception. */
161 STD_EXCEPTION(0x300, DataStorage, UnknownException)
163 /* Instruction Storage exception. */
164 STD_EXCEPTION(0x400, InstStorage, UnknownException)
166 /* External Interrupt exception. */
167 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
169 /* Alignment exception. */
172 EXCEPTION_PROLOG(SRR0, SRR1)
177 addi r3,r1,STACK_FRAME_OVERHEAD
179 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
180 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
181 lwz r6,GOT(transfer_to_handler)
185 .long AlignmentException - _start + EXC_OFF_SYS_RESET
186 .long int_return - _start + EXC_OFF_SYS_RESET
188 /* Program check exception */
191 EXCEPTION_PROLOG(SRR0, SRR1)
192 addi r3,r1,STACK_FRAME_OVERHEAD
194 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
195 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
196 lwz r6,GOT(transfer_to_handler)
200 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
201 .long int_return - _start + EXC_OFF_SYS_RESET
203 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
205 /* I guess we could implement decrementer, and may have
206 * to someday for timekeeping.
208 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
210 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
211 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
212 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
213 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
215 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
216 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
218 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
219 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
220 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
224 * This exception occurs when the program counter matches the
225 * Instruction Address Breakpoint Register (IABR).
227 * I want the cpu to halt if this occurs so I can hunt around
228 * with the debugger and look at things.
230 * When DEBUG is defined, both machine check enable (in the MSR)
231 * and checkstop reset enable (in the reset mode register) are
232 * turned off and so a checkstop condition will result in the cpu
235 * I force the cpu into a checkstop condition by putting an illegal
236 * instruction here (at least this is the theory).
238 * well - that didnt work, so just do an infinite loop!
242 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
244 STD_EXCEPTION(0x1400, SMI, UnknownException)
246 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
247 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
248 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
249 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
250 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
251 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
252 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
253 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
254 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
255 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
256 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
257 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
258 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
259 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
260 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
261 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
262 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
263 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
264 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
265 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
266 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
267 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
268 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
269 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
270 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
271 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
272 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
275 .globl _end_of_vectors
281 * This code finishes saving the registers to the exception frame
282 * and jumps to the appropriate handler for the exception.
283 * Register r21 is pointer into trap frame, r1 has new stack pointer.
285 .globl transfer_to_handler
296 andi. r24,r23,0x3f00 /* get vector offset */
300 lwz r24,0(r23) /* virtual address of handler */
301 lwz r23,4(r23) /* where to go when done */
306 rfi /* jump to handler, enable MMU */
309 mfmsr r28 /* Disable interrupts */
313 SYNC /* Some chip revs need this... */
328 lwz r2,_NIP(r1) /* Restore environment */
339 * This code initialises the MPC8220 processor core
340 * (conforms to PowerPC 603e spec)
341 * Note: expects original MSR contents to be in r5.
344 .globl init_8220_core
347 /* Initialize machine status; enable machine check interrupt */
348 /*--------------------------------------------------------------*/
350 li r3, MSR_KERNEL /* Set ME and RI flags */
351 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
353 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
355 SYNC /* Some chip revs need this... */
358 mtspr SRR1, r3 /* Make SRR1 match MSR */
360 /* Initialize the Hardware Implementation-dependent Registers */
361 /* HID0 also contains cache control */
362 /*--------------------------------------------------------------*/
364 lis r3, CFG_HID0_INIT@h
365 ori r3, r3, CFG_HID0_INIT@l
369 lis r3, CFG_HID0_FINAL@h
370 ori r3, r3, CFG_HID0_FINAL@l
374 /* Enable Extra BATs */
375 mfspr r3, 1011 /* HID2 */
382 /* clear all BAT's */
383 /*--------------------------------------------------------------*/
420 /* invalidate all tlb's */
422 /* From the 603e User Manual: "The 603e provides the ability to */
423 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
424 /* instruction invalidates the TLB entry indexed by the EA, and */
425 /* operates on both the instruction and data TLBs simultaneously*/
426 /* invalidating four TLB entries (both sets in each TLB). The */
427 /* index corresponds to bits 15-19 of the EA. To invalidate all */
428 /* entries within both TLBs, 32 tlbie instructions should be */
429 /* issued, incrementing this field by one each time." */
431 /* "Note that the tlbia instruction is not implemented on the */
434 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
435 /* incrementing by 0x1000 each time. The code below is sort of */
436 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
438 /*--------------------------------------------------------------*/
449 /*--------------------------------------------------------------*/
455 * Note: requires that all cache bits in
456 * HID0 are in the low half word.
461 ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */
462 rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
465 * The setting of the instruction cache enable (ICE) bit must be
466 * preceded by an isync instruction to prevent the cache from being
467 * enabled or disabled while an instruction access is in progress.
470 mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
471 mtspr HID0, r3 /* using 2 consec instructions */
475 .globl icache_disable
478 rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */
486 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
492 ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */
493 rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */
495 /* Enable address translation in MSR bit */
501 * The setting of the instruction cache enable (ICE) bit must be
502 * preceded by an isync instruction to prevent the cache from being
503 * enabled or disabled while an instruction access is in progress.
506 mtspr HID0, r4 /* Enable Data Cache & Inval cache*/
507 mtspr HID0, r3 /* using 2 consec instructions */
511 .globl dcache_disable
514 rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */
522 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
530 /*------------------------------------------------------------------------------*/
533 * void relocate_code (addr_sp, gd, addr_moni)
535 * This "function" does not return, instead it continues in RAM
536 * after relocating the monitor code.
540 * r5 = length in bytes
545 mr r1, r3 /* Set new stack pointer */
546 mr r9, r4 /* Save copy of Global Data pointer */
547 mr r10, r5 /* Save copy of Destination Address */
549 mr r3, r5 /* Destination Address */
550 lis r4, CFG_MONITOR_BASE@h /* Source Address */
551 ori r4, r4, CFG_MONITOR_BASE@l
552 lwz r5, GOT(__init_end)
554 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
559 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
565 /* First our own GOT */
567 /* then the one used by the C code */
577 beq cr1,4f /* In place copy is not necessary */
578 beq 7f /* Protect against 0 count */
597 * Now flush the cache: note that we must start from a cache aligned
598 * address. Otherwise we might miss one cache line.
602 beq 7f /* Always flush prefetch queue in any case */
605 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
606 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
614 sync /* Wait for all dcbst to complete on bus */
615 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
616 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
624 7: sync /* Wait for all icbi to complete on bus */
628 * We are done. Do not return, instead branch to second part of board
629 * initialization, now running from RAM.
632 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
639 * Relocation Function, r14 point to got2+0x8000
641 * Adjust got2 pointers, no need to check for 0, this code
642 * already puts a few entries in the table.
644 li r0,__got2_entries@sectoff@l
645 la r3,GOT(_GOT2_TABLE_)
646 lwz r11,GOT(_GOT2_TABLE_)
656 * Now adjust the fixups and the pointers to the fixups
657 * in case we need to move ourselves again.
659 2: li r0,__fixup_entries@sectoff@l
660 lwz r3,GOT(_FIXUP_TABLE_)
674 * Now clear BSS segment
676 lwz r3,GOT(__bss_start)
690 mr r3, r9 /* Global Data pointer */
691 mr r4, r10 /* Destination Address */
695 * Copy exception vector code to low memory
698 * r7: source address, r8: end address, r9: target address
703 lwz r8, GOT(_end_of_vectors)
705 li r9, 0x100 /* reset vector always at 0x100 */
708 bgelr /* return if r7>=r8 - just in case */
710 mflr r4 /* save link register */
720 * relocate `hdlr' and `int_return' entries
722 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
723 li r8, Alignment - _start + EXC_OFF_SYS_RESET
726 addi r7, r7, 0x100 /* next exception vector */
730 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
733 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
736 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
737 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
740 addi r7, r7, 0x100 /* next exception vector */
744 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
745 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
748 addi r7, r7, 0x100 /* next exception vector */
752 mfmsr r3 /* now that the vectors have */
753 lis r7, MSR_IP@h /* relocated into low memory */
754 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
755 andc r3, r3, r7 /* (if it was on) */
756 SYNC /* Some chip revs need this... */
760 mtlr r4 /* restore link register */
764 * Function: relocate entries for one exception vector
767 lwz r0, 0(r7) /* hdlr ... */
768 add r0, r0, r3 /* ... += dest_addr */
771 lwz r0, 4(r7) /* int_return ... */
772 add r0, r0, r3 /* ... += dest_addr */