2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8220 CPUs
30 #include <timestamp.h>
33 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 #include <ppc_asm.tmpl>
38 #include <asm/cache.h>
41 #ifndef CONFIG_IDENT_STRING
42 #define CONFIG_IDENT_STRING ""
45 /* We don't want the MMU yet.
48 /* Floating Point enable, Machine Check and Recoverable Interr. */
50 #define MSR_KERNEL (MSR_FP|MSR_RI)
52 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56 * Set up GOT: Global Offset Table
58 * Use r14 to access the GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
71 GOT_ENTRY(__bss_start)
81 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
91 li r21, BOOTFLAG_COLD /* Normal Power-On */
95 . = EXC_OFF_SYS_RESET + 0x10
99 li r21, BOOTFLAG_WARM /* Software reboot */
104 mfmsr r5 /* save msr contents */
106 /* replace default MBAR base address from 0x80000000
109 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
110 lis r3, CONFIG_SYS_MBAR@h
111 ori r3, r3, CONFIG_SYS_MBAR@l
113 /* MBAR is mirrored into the MBAR SPR */
116 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
118 #endif /* CONFIG_SYS_DEFAULT_MBAR */
120 /* Initialise the MPC8220 processor core */
121 /*--------------------------------------------------------------*/
125 /* initialize some things that are hard to access from C */
126 /*--------------------------------------------------------------*/
128 /* set up stack in on-chip SRAM */
129 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
130 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
131 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
133 li r0, 0 /* Make room for stack frame header and */
134 stwu r0, -4(r1) /* clear final stack frame so that */
135 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
137 /* let the C-code set up the rest */
139 /* Be careful to keep code relocatable ! */
140 /*--------------------------------------------------------------*/
142 GET_GOT /* initialize GOT access */
145 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
149 bl board_init_f /* run 1st part of board init code (in Flash)*/
155 .globl _start_of_vectors
159 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
161 /* Data Storage exception. */
162 STD_EXCEPTION(0x300, DataStorage, UnknownException)
164 /* Instruction Storage exception. */
165 STD_EXCEPTION(0x400, InstStorage, UnknownException)
167 /* External Interrupt exception. */
168 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
170 /* Alignment exception. */
173 EXCEPTION_PROLOG(SRR0, SRR1)
178 addi r3,r1,STACK_FRAME_OVERHEAD
180 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
181 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
182 lwz r6,GOT(transfer_to_handler)
186 .long AlignmentException - _start + EXC_OFF_SYS_RESET
187 .long int_return - _start + EXC_OFF_SYS_RESET
189 /* Program check exception */
192 EXCEPTION_PROLOG(SRR0, SRR1)
193 addi r3,r1,STACK_FRAME_OVERHEAD
195 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
196 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
197 lwz r6,GOT(transfer_to_handler)
201 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
202 .long int_return - _start + EXC_OFF_SYS_RESET
204 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
206 /* I guess we could implement decrementer, and may have
207 * to someday for timekeeping.
209 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
211 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
212 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
213 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
214 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
216 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
217 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
219 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
220 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
221 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
225 * This exception occurs when the program counter matches the
226 * Instruction Address Breakpoint Register (IABR).
228 * I want the cpu to halt if this occurs so I can hunt around
229 * with the debugger and look at things.
231 * When DEBUG is defined, both machine check enable (in the MSR)
232 * and checkstop reset enable (in the reset mode register) are
233 * turned off and so a checkstop condition will result in the cpu
236 * I force the cpu into a checkstop condition by putting an illegal
237 * instruction here (at least this is the theory).
239 * well - that didnt work, so just do an infinite loop!
243 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
245 STD_EXCEPTION(0x1400, SMI, UnknownException)
247 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
248 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
249 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
250 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
251 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
252 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
253 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
254 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
255 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
256 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
257 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
258 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
259 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
260 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
261 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
262 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
263 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
264 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
265 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
266 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
267 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
268 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
269 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
270 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
271 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
272 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
273 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
276 .globl _end_of_vectors
282 * This code finishes saving the registers to the exception frame
283 * and jumps to the appropriate handler for the exception.
284 * Register r21 is pointer into trap frame, r1 has new stack pointer.
286 .globl transfer_to_handler
297 andi. r24,r23,0x3f00 /* get vector offset */
301 lwz r24,0(r23) /* virtual address of handler */
302 lwz r23,4(r23) /* where to go when done */
307 rfi /* jump to handler, enable MMU */
310 mfmsr r28 /* Disable interrupts */
314 SYNC /* Some chip revs need this... */
329 lwz r2,_NIP(r1) /* Restore environment */
340 * This code initialises the MPC8220 processor core
341 * (conforms to PowerPC 603e spec)
342 * Note: expects original MSR contents to be in r5.
345 .globl init_8220_core
348 /* Initialize machine status; enable machine check interrupt */
349 /*--------------------------------------------------------------*/
351 li r3, MSR_KERNEL /* Set ME and RI flags */
352 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
354 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
356 SYNC /* Some chip revs need this... */
359 mtspr SRR1, r3 /* Make SRR1 match MSR */
361 /* Initialize the Hardware Implementation-dependent Registers */
362 /* HID0 also contains cache control */
363 /*--------------------------------------------------------------*/
365 lis r3, CONFIG_SYS_HID0_INIT@h
366 ori r3, r3, CONFIG_SYS_HID0_INIT@l
370 lis r3, CONFIG_SYS_HID0_FINAL@h
371 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
375 /* Enable Extra BATs */
376 mfspr r3, 1011 /* HID2 */
383 /* clear all BAT's */
384 /*--------------------------------------------------------------*/
421 /* invalidate all tlb's */
423 /* From the 603e User Manual: "The 603e provides the ability to */
424 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
425 /* instruction invalidates the TLB entry indexed by the EA, and */
426 /* operates on both the instruction and data TLBs simultaneously*/
427 /* invalidating four TLB entries (both sets in each TLB). The */
428 /* index corresponds to bits 15-19 of the EA. To invalidate all */
429 /* entries within both TLBs, 32 tlbie instructions should be */
430 /* issued, incrementing this field by one each time." */
432 /* "Note that the tlbia instruction is not implemented on the */
435 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
436 /* incrementing by 0x1000 each time. The code below is sort of */
437 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
439 /*--------------------------------------------------------------*/
450 /*--------------------------------------------------------------*/
456 * Note: requires that all cache bits in
457 * HID0 are in the low half word.
462 ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */
463 rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
466 * The setting of the instruction cache enable (ICE) bit must be
467 * preceded by an isync instruction to prevent the cache from being
468 * enabled or disabled while an instruction access is in progress.
471 mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
472 mtspr HID0, r3 /* using 2 consec instructions */
476 .globl icache_disable
479 rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */
487 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
493 ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */
494 rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */
496 /* Enable address translation in MSR bit */
502 * The setting of the instruction cache enable (ICE) bit must be
503 * preceded by an isync instruction to prevent the cache from being
504 * enabled or disabled while an instruction access is in progress.
507 mtspr HID0, r4 /* Enable Data Cache & Inval cache*/
508 mtspr HID0, r3 /* using 2 consec instructions */
512 .globl dcache_disable
515 rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */
523 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
531 /*------------------------------------------------------------------------------*/
534 * void relocate_code (addr_sp, gd, addr_moni)
536 * This "function" does not return, instead it continues in RAM
537 * after relocating the monitor code.
541 * r5 = length in bytes
546 mr r1, r3 /* Set new stack pointer */
547 mr r9, r4 /* Save copy of Global Data pointer */
548 mr r10, r5 /* Save copy of Destination Address */
550 mr r3, r5 /* Destination Address */
551 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
552 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
553 lwz r5, GOT(__init_end)
555 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
560 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
566 /* First our own GOT */
568 /* then the one used by the C code */
578 beq cr1,4f /* In place copy is not necessary */
579 beq 7f /* Protect against 0 count */
598 * Now flush the cache: note that we must start from a cache aligned
599 * address. Otherwise we might miss one cache line.
603 beq 7f /* Always flush prefetch queue in any case */
606 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
607 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
615 sync /* Wait for all dcbst to complete on bus */
616 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
617 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
625 7: sync /* Wait for all icbi to complete on bus */
629 * We are done. Do not return, instead branch to second part of board
630 * initialization, now running from RAM.
633 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
640 * Relocation Function, r14 point to got2+0x8000
642 * Adjust got2 pointers, no need to check for 0, this code
643 * already puts a few entries in the table.
645 li r0,__got2_entries@sectoff@l
646 la r3,GOT(_GOT2_TABLE_)
647 lwz r11,GOT(_GOT2_TABLE_)
657 * Now adjust the fixups and the pointers to the fixups
658 * in case we need to move ourselves again.
660 2: li r0,__fixup_entries@sectoff@l
661 lwz r3,GOT(_FIXUP_TABLE_)
675 * Now clear BSS segment
677 lwz r3,GOT(__bss_start)
691 mr r3, r9 /* Global Data pointer */
692 mr r4, r10 /* Destination Address */
696 * Copy exception vector code to low memory
699 * r7: source address, r8: end address, r9: target address
704 lwz r8, GOT(_end_of_vectors)
706 li r9, 0x100 /* reset vector always at 0x100 */
709 bgelr /* return if r7>=r8 - just in case */
711 mflr r4 /* save link register */
721 * relocate `hdlr' and `int_return' entries
723 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
724 li r8, Alignment - _start + EXC_OFF_SYS_RESET
727 addi r7, r7, 0x100 /* next exception vector */
731 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
734 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
737 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
738 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
741 addi r7, r7, 0x100 /* next exception vector */
745 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
746 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
749 addi r7, r7, 0x100 /* next exception vector */
753 mfmsr r3 /* now that the vectors have */
754 lis r7, MSR_IP@h /* relocated into low memory */
755 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
756 andc r3, r3, r7 /* (if it was on) */
757 SYNC /* Some chip revs need this... */
761 mtlr r4 /* restore link register */
765 * Function: relocate entries for one exception vector
768 lwz r0, 0(r7) /* hdlr ... */
769 add r0, r0, r3 /* ... += dest_addr */
772 lwz r0, 4(r7) /* int_return ... */
773 add r0, r0, r3 /* ... += dest_addr */