3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
19 /*#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC8220_FEC)*/
22 #if (CONFIG_COMMANDS & CFG_CMD_NET)
25 static void tfifo_print (mpc8220_fec_priv * fec);
26 static void rfifo_print (mpc8220_fec_priv * fec);
30 static u32 local_crc32 (char *string, unsigned int crc_value, int len);
34 u8 data[1500]; /* actual data */
35 int length; /* actual length */
36 int used; /* buffer in use or not */
37 u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
40 /********************************************************************/
42 static void mpc8220_fec_phydump (void)
45 u8 phyAddr = CONFIG_PHY_ADDR;
47 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
48 /* regs to print: 0...7, 16...19, 21, 23, 24 */
49 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
50 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
52 /* regs to print: 0...8, 16...20 */
53 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
54 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
58 for (i = 0; i < 32; i++) {
60 miiphy_read (phyAddr, i, &phyStatus);
61 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
67 /********************************************************************/
68 static int mpc8220_fec_rbd_init (mpc8220_fec_priv * fec)
74 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
76 data = (char *) malloc (FEC_MAX_PKT_SIZE);
78 printf ("RBD INIT FAILED\n");
81 fec->rbdBase[ix].dataPointer = (u32) data;
83 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
84 fec->rbdBase[ix].dataLength = 0;
89 * have the last RBD to close the ring
91 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
97 /********************************************************************/
98 static void mpc8220_fec_tbd_init (mpc8220_fec_priv * fec)
102 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
103 fec->tbdBase[ix].status = 0;
107 * Have the last TBD to close the ring
109 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
112 * Initialize some indices
115 fec->usedTbdIndex = 0;
116 fec->cleanTbdNum = FEC_TBD_NUM;
119 /********************************************************************/
120 static void mpc8220_fec_rbd_clean (mpc8220_fec_priv * fec, FEC_RBD * pRbd)
123 * Reset buffer descriptor as empty
125 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
126 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
128 pRbd->status = FEC_RBD_EMPTY;
130 pRbd->dataLength = 0;
133 * Now, we have an empty RxBD, restart the SmartDMA receive task
135 DMA_TASK_ENABLE (FEC_RECV_TASK_NO);
140 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
143 /********************************************************************/
144 static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv * fec)
149 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
150 fec->cleanTbdNum, fec->usedTbdIndex);
154 * process all the consumed TBDs
156 while (fec->cleanTbdNum < FEC_TBD_NUM) {
157 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
158 if (pUsedTbd->status & FEC_TBD_READY) {
160 printf ("Cannot clean TBD %d, in use\n",
167 * clean this buffer descriptor
169 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
170 pUsedTbd->status = FEC_TBD_WRAP;
172 pUsedTbd->status = 0;
175 * update some indeces for a correct handling of the TBD ring
178 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
182 /********************************************************************/
183 static void mpc8220_fec_set_hwaddr (mpc8220_fec_priv * fec, char *mac)
185 u8 currByte; /* byte for which to compute the CRC */
186 int byte; /* loop - counter */
187 int bit; /* loop - counter */
188 u32 crc = 0xffffffff; /* initial value */
191 * The algorithm used is the following:
192 * we loop on each of the six bytes of the provided address,
193 * and we compute the CRC by left-shifting the previous
194 * value by one position, so that each bit in the current
195 * byte of the address may contribute the calculation. If
196 * the latter and the MSB in the CRC are different, then
197 * the CRC value so computed is also ex-ored with the
198 * "polynomium generator". The current byte of the address
199 * is also shifted right by one bit at each iteration.
200 * This is because the CRC generatore in hardware is implemented
201 * as a shift-register with as many ex-ores as the radixes
202 * in the polynomium. This suggests that we represent the
203 * polynomiumm itself as a 32-bit constant.
205 for (byte = 0; byte < 6; byte++) {
206 currByte = mac[byte];
207 for (bit = 0; bit < 8; bit++) {
208 if ((currByte & 0x01) ^ (crc & 0x01)) {
210 crc = crc ^ 0xedb88320;
221 * Set individual hash table register
224 fec->eth->iaddr1 = (1 << (crc - 32));
225 fec->eth->iaddr2 = 0;
227 fec->eth->iaddr1 = 0;
228 fec->eth->iaddr2 = (1 << crc);
232 * Set physical address
235 (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
236 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
239 /********************************************************************/
240 static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
242 mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
243 struct mpc8220_dma *dma = (struct mpc8220_dma *) MMAP_DMA;
244 const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
247 printf ("mpc8220_fec_init... Begin\n");
251 * Initialize RxBD/TxBD rings
253 mpc8220_fec_rbd_init (fec);
254 mpc8220_fec_tbd_init (fec);
257 * Set up Pin Muxing for FEC 1
259 *(vu_long *) MMAP_PCFG = 0;
260 *(vu_long *) (MMAP_PCFG + 4) = 0;
262 * Clear FEC-Lite interrupt event register(IEVENT)
264 fec->eth->ievent = 0xffffffff;
267 * Set interrupt mask register
269 fec->eth->imask = 0x00000000;
272 * Set FEC-Lite receive control register(R_CNTRL):
274 if (fec->xcv_type == SEVENWIRE) {
276 * Frame length=1518; 7-wire mode
278 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
281 * Frame length=1518; MII mode;
283 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
286 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
287 if (fec->xcv_type != SEVENWIRE) {
289 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
290 * and do not drop the Preamble.
293 /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */
294 /* No MII for 7-wire mode */
295 fec->eth->mii_speed = 0x00000030;
299 * Set Opcode/Pause Duration Register
301 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
304 * Set Rx FIFO alarm and granularity value
306 fec->eth->rfifo_cntrl = 0x0c000000;
307 fec->eth->rfifo_alarm = 0x0000030c;
309 if (fec->eth->rfifo_status & 0x00700000) {
310 printf ("mpc8220_fec_init() RFIFO error\n");
315 * Set Tx FIFO granularity value
317 /*fec->eth->tfifo_cntrl = 0x0c000000; */ /*tbd - rtm */
318 fec->eth->tfifo_cntrl = 0x0e000000;
320 printf ("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
321 printf ("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
325 * Set transmit fifo watermark register(X_WMRK), default = 64
327 fec->eth->tfifo_alarm = 0x00000080;
328 fec->eth->x_wmrk = 0x2;
331 * Set individual address filter for unicast address
332 * and set physical address registers.
334 mpc8220_fec_set_hwaddr (fec, dev->enetaddr);
337 * Set multicast address filter
339 fec->eth->gaddr1 = 0x00000000;
340 fec->eth->gaddr2 = 0x00000000;
343 * Turn ON cheater FSM: ????
345 fec->eth->xmit_fsm = 0x03000000;
348 /*#if defined(CONFIG_MPC5200)*/
350 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
351 * work w/ the current receive task.
353 dma->PtdCntrl |= 0x00000001;
357 * Set priority of different initiators
359 dma->IPR0 = 7; /* always */
360 dma->IPR3 = 6; /* Eth RX */
361 dma->IPR4 = 5; /* Eth Tx */
364 * Clear SmartDMA task interrupt pending bits
366 DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
369 * Initialize SmartDMA parameters stored in SRAM
371 *(int *) FEC_TBD_BASE = (int) fec->tbdBase;
372 *(int *) FEC_RBD_BASE = (int) fec->rbdBase;
373 *(int *) FEC_TBD_NEXT = (int) fec->tbdBase;
374 *(int *) FEC_RBD_NEXT = (int) fec->rbdBase;
376 if (fec->xcv_type != SEVENWIRE) {
378 * Initialize PHY(LXT971A):
380 * Generally, on power up, the LXT971A reads its configuration
381 * pins to check for forced operation, If not cofigured for
382 * forced operation, it uses auto-negotiation/parallel detection
383 * to automatically determine line operating conditions.
384 * If the PHY device on the other side of the link supports
385 * auto-negotiation, the LXT971A auto-negotiates with it
386 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
387 * support auto-negotiation, the LXT971A automatically detects
388 * the presence of either link pulses(10Mbps PHY) or Idle
389 * symbols(100Mbps) and sets its operating conditions accordingly.
391 * When auto-negotiation is controlled by software, the following
392 * steps are recommended.
395 * The physical address is dependent on hardware configuration.
402 * Reset PHY, then delay 300ns
404 miiphy_write (phyAddr, 0x0, 0x8000);
407 if (fec->xcv_type == MII10) {
409 * Force 10Base-T, FDX operation
412 printf ("Forcing 10 Mbps ethernet link... ");
414 miiphy_read (phyAddr, 0x1, &phyStatus);
416 miiphy_write(fec, phyAddr, 0x0, 0x0100);
418 miiphy_write (phyAddr, 0x0, 0x0180);
421 do { /* wait for link status to go down */
423 if ((timeout--) == 0) {
425 printf ("hmmm, should not have waited...");
429 miiphy_read (phyAddr, 0x1, &phyStatus);
433 } while ((phyStatus & 0x0004)); /* !link up */
436 do { /* wait for link status to come back up */
438 if ((timeout--) == 0) {
439 printf ("failed. Link is down.\n");
442 miiphy_read (phyAddr, 0x1, &phyStatus);
446 } while (!(phyStatus & 0x0004)); /* !link up */
451 } else { /* MII100 */
453 * Set the auto-negotiation advertisement register bits
455 miiphy_write (phyAddr, 0x4, 0x01e1);
458 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
460 miiphy_write (phyAddr, 0x0, 0x1200);
463 * Wait for AN completion
469 if ((timeout--) == 0) {
471 printf ("PHY auto neg 0 failed...\n");
476 if (miiphy_read (phyAddr, 0x1, &phyStatus) !=
479 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
483 } while (!(phyStatus & 0x0004));
486 printf ("PHY auto neg complete! \n");
493 * Enable FEC-Lite controller
495 fec->eth->ecntrl |= 0x00000006;
498 if (fec->xcv_type != SEVENWIRE)
499 mpc8220_fec_phydump ();
503 * Enable SmartDMA receive task
505 DMA_TASK_ENABLE (FEC_RECV_TASK_NO);
508 printf ("mpc8220_fec_init... Done \n");
514 /********************************************************************/
515 static void mpc8220_fec_halt (struct eth_device *dev)
517 mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
518 int counter = 0xffff;
521 if (fec->xcv_type != SEVENWIRE)
522 mpc8220_fec_phydump ();
526 * mask FEC chip interrupts
531 * issue graceful stop command to the FEC transmitter if necessary
533 fec->eth->x_cntrl |= 0x00000001;
536 * wait for graceful stop to register
538 while ((counter--) && (!(fec->eth->ievent & 0x10000000)));
541 * Disable SmartDMA tasks
543 DMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
544 DMA_TASK_DISABLE (FEC_RECV_TASK_NO);
547 * Disable the Ethernet Controller
549 fec->eth->ecntrl &= 0xfffffffd;
552 * Clear FIFO status registers
554 fec->eth->rfifo_status &= 0x00700000;
555 fec->eth->tfifo_status &= 0x00700000;
557 fec->eth->reset_cntrl = 0x01000000;
560 * Issue a reset command to the FEC chip
562 fec->eth->ecntrl |= 0x1;
565 * wait at least 16 clock cycles
570 printf ("Ethernet task stopped\n");
575 /********************************************************************/
577 static void tfifo_print (mpc8220_fec_priv * fec)
579 u16 phyAddr = CONFIG_PHY_ADDR;
582 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
583 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
585 miiphy_read (phyAddr, 0x1, &phyStatus);
586 printf ("\nphyStatus: 0x%04x\n", phyStatus);
587 printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
588 printf ("ievent: 0x%08x\n", fec->eth->ievent);
589 printf ("x_status: 0x%08x\n", fec->eth->x_status);
590 printf ("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
592 printf (" control 0x%08x\n", fec->eth->tfifo_cntrl);
593 printf (" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
594 printf (" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
595 printf (" alarm 0x%08x\n", fec->eth->tfifo_alarm);
596 printf (" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
597 printf (" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
601 static void rfifo_print (mpc8220_fec_priv * fec)
603 u16 phyAddr = CONFIG_PHY_ADDR;
606 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
607 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
609 miiphy_read (phyAddr, 0x1, &phyStatus);
610 printf ("\nphyStatus: 0x%04x\n", phyStatus);
611 printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
612 printf ("ievent: 0x%08x\n", fec->eth->ievent);
613 printf ("x_status: 0x%08x\n", fec->eth->x_status);
614 printf ("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
616 printf (" control 0x%08x\n", fec->eth->rfifo_cntrl);
617 printf (" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
618 printf (" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
619 printf (" alarm 0x%08x\n", fec->eth->rfifo_alarm);
620 printf (" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
621 printf (" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
626 /********************************************************************/
628 static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
632 * This routine transmits one frame. This routine only accepts
633 * 6-byte Ethernet addresses.
635 mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
639 printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
644 * Clear Tx BD ring at first
646 mpc8220_fec_tbd_scrub (fec);
649 * Check for valid length of data.
651 if ((data_length > 1500) || (data_length <= 0)) {
656 * Check the number of vacant TxBDs.
658 if (fec->cleanTbdNum < 1) {
660 printf ("No available TxBDs ...\n");
666 * Get the first TxBD to send the mac header
668 pTbd = &fec->tbdBase[fec->tbdIndex];
669 pTbd->dataLength = data_length;
670 pTbd->dataPointer = (u32) eth_data;
671 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
672 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
675 printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
681 if (fec->xcv_type != SEVENWIRE) {
684 miiphy_read (0, 0x1, &phyStatus);
688 * Enable SmartDMA transmit task
695 DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
705 fec->cleanTbdNum -= 1;
707 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
708 printf ("smartDMA ethernet Tx task enabled\n");
711 * wait until frame is sent .
713 while (pTbd->status & FEC_TBD_READY) {
716 printf ("TDB status = %04x\n", pTbd->status);
724 /********************************************************************/
725 static int mpc8220_fec_recv (struct eth_device *dev)
728 * This command pulls one frame from the card
730 mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv;
731 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
732 unsigned long ievent;
733 int frame_length, len = 0;
737 printf ("mpc8220_fec_recv %d Start...\n", fec->rbdIndex);
744 * Check if any critical events have happened
746 ievent = fec->eth->ievent;
747 fec->eth->ievent = ievent;
748 if (ievent & 0x20060000) {
749 /* BABT, Rx/Tx FIFO errors */
750 mpc8220_fec_halt (dev);
751 mpc8220_fec_init (dev, NULL);
754 if (ievent & 0x80000000) {
755 /* Heartbeat error */
756 fec->eth->x_cntrl |= 0x00000001;
758 if (ievent & 0x10000000) {
759 /* Graceful stop complete */
760 if (fec->eth->x_cntrl & 0x00000001) {
761 mpc8220_fec_halt (dev);
762 fec->eth->x_cntrl &= ~0x00000001;
763 mpc8220_fec_init (dev, NULL);
767 if (!(pRbd->status & FEC_RBD_EMPTY)) {
768 if ((pRbd->status & FEC_RBD_LAST)
769 && !(pRbd->status & FEC_RBD_ERR)
770 && ((pRbd->dataLength - 4) > 14)) {
773 * Get buffer address and size
775 frame = (NBUF *) pRbd->dataPointer;
776 frame_length = pRbd->dataLength - 4;
782 printf ("recv data hdr:");
783 for (i = 0; i < 14; i++)
784 printf ("%x ", *(frame->head + i));
789 * Fill the buffer and pass it to upper layers
791 /* memcpy(buff, frame->head, 14);
792 memcpy(buff + 14, frame->data, frame_length);*/
793 NetReceive ((volatile uchar *) pRbd->dataPointer,
798 * Reset buffer descriptor as empty
800 mpc8220_fec_rbd_clean (fec, pRbd);
802 DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
807 /********************************************************************/
808 int mpc8220_fec_initialize (bd_t * bis)
810 mpc8220_fec_priv *fec;
812 #ifdef CONFIG_HAS_ETH1
813 mpc8220_fec_priv *fec2;
815 struct eth_device *dev;
817 char env_enetaddr[6];
819 #ifdef CONFIG_HAS_ETH1
820 char env_enet1addr[6];
824 fec = (mpc8220_fec_priv *) malloc (sizeof (*fec));
825 dev = (struct eth_device *) malloc (sizeof (*dev));
826 memset (dev, 0, sizeof *dev);
828 fec->eth = (ethernet_regs *) MMAP_FEC1;
829 #ifdef CONFIG_HAS_ETH1
830 fec2 = (mpc8220_fec_priv *) malloc (sizeof (*fec));
831 fec2->eth = (ethernet_regs *) MMAP_FEC2;
833 fec->tbdBase = (FEC_TBD *) FEC_BD_BASE;
835 (FEC_RBD *) (FEC_BD_BASE + FEC_TBD_NUM * sizeof (FEC_TBD));
836 fec->xcv_type = MII100;
838 dev->priv = (void *) fec;
839 dev->iobase = MMAP_FEC1;
840 dev->init = mpc8220_fec_init;
841 dev->halt = mpc8220_fec_halt;
842 dev->send = mpc8220_fec_send;
843 dev->recv = mpc8220_fec_recv;
845 sprintf (dev->name, "FEC ETHERNET");
849 * Try to set the mac address now. The fec mac address is
850 * a garbage after reset. When not using fec for booting
851 * the Linux fec driver will try to work with this garbage.
853 tmp = getenv ("ethaddr");
855 for (i = 0; i < 6; i++) {
857 tmp ? simple_strtoul (tmp, &end, 16) : 0;
859 tmp = (*end) ? end + 1 : end;
861 mpc8220_fec_set_hwaddr (fec, env_enetaddr);
863 #ifdef CONFIG_HAS_ETH1
864 tmp = getenv ("eth1addr");
866 for (i = 0; i < 6; i++) {
868 tmp ? simple_strtoul (tmp, &end, 16) : 0;
870 tmp = (*end) ? end + 1 : end;
872 mpc8220_fec_set_hwaddr (fec2, env_enet1addr);
879 /* MII-interface related functions */
880 /********************************************************************/
881 int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
883 ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
884 u32 reg; /* convenient holder for the PHY register */
885 u32 phy; /* convenient holder for the PHY */
886 int timeout = 0xffff;
889 * reading from any PHY's register is done by properly
890 * programming the FEC's MII data register.
892 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
893 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
896 (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy
900 * wait for the related interrupt
902 while ((timeout--) && (!(eth->ievent & 0x00800000)));
906 printf ("Read MDIO failed...\n");
912 * clear mii interrupt bit
914 eth->ievent = 0x00800000;
917 * it's now safe to read the PHY's register
919 *retVal = (u16) eth->mii_data;
924 /********************************************************************/
925 int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
927 ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
928 u32 reg; /* convenient holder for the PHY register */
929 u32 phy; /* convenient holder for the PHY */
930 int timeout = 0xffff;
932 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
933 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
935 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
936 FEC_MII_DATA_TA | phy | reg | data);
939 * wait for the MII interrupt
941 while ((timeout--) && (!(eth->ievent & 0x00800000)));
945 printf ("Write MDIO failed...\n");
951 * clear MII interrupt bit
953 eth->ievent = 0x00800000;
959 static u32 local_crc32 (char *string, unsigned int crc_value, int len)
963 unsigned int crc, count;
969 * crc = 0xffffffff; * The initialized value should be 0xffffffff
973 for (i = len; --i >= 0;) {
975 for (count = 0; count < 8; count++) {
976 if ((c & 0x01) ^ (crc & 0x01)) {
978 crc = crc ^ 0xedb88320;
987 * In big endian system, do byte swaping for crc value
993 #endif /* CONFIG_MPC8220_FEC */