2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC5xxx CPUs
30 #include <timestamp.h>
33 #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
34 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
36 #include <ppc_asm.tmpl>
39 #include <asm/cache.h>
42 #ifndef CONFIG_IDENT_STRING
43 #define CONFIG_IDENT_STRING ""
46 /* We don't want the MMU yet.
49 /* Floating Point enable, Machine Check and Recoverable Interr. */
51 #define MSR_KERNEL (MSR_FP|MSR_RI)
53 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
57 * Set up GOT: Global Offset Table
59 * Use r14 to access the GOT
62 GOT_ENTRY(_GOT2_TABLE_)
63 GOT_ENTRY(_FIXUP_TABLE_)
66 GOT_ENTRY(_start_of_vectors)
67 GOT_ENTRY(_end_of_vectors)
68 GOT_ENTRY(transfer_to_handler)
72 GOT_ENTRY(__bss_start)
82 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
83 .ascii CONFIG_IDENT_STRING, "\0"
92 li r21, BOOTFLAG_COLD /* Normal Power-On */
96 . = EXC_OFF_SYS_RESET + 0x10
100 li r21, BOOTFLAG_WARM /* Software reboot */
105 mfmsr r5 /* save msr contents */
107 /* Move CSBoot and adjust instruction pointer */
108 /*--------------------------------------------------------------*/
110 #if defined(CONFIG_SYS_LOWBOOT)
111 # if defined(CONFIG_SYS_RAMBOOT)
112 # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
113 # endif /* CONFIG_SYS_RAMBOOT */
114 # if defined(CONFIG_MGT5100)
115 # error CONFIG_SYS_LOWBOOT is incompatible with MGT5100
116 # endif /* CONFIG_MGT5100 */
117 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
118 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
119 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
120 stw r3, 0x4(r4) /* CS0 start */
121 lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
122 ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
123 stw r3, 0x8(r4) /* CS0 stop */
125 ori r3, r3, 0x02010000@l
126 stw r3, 0x54(r4) /* CS0 and Boot enable */
128 lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */
129 ori r3, r3, lowboot_reentry@l /* to the address space the linker used */
134 lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
135 ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
136 stw r3, 0x4c(r4) /* Boot start */
137 lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
138 ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
139 stw r3, 0x50(r4) /* Boot stop */
141 ori r3, r3, 0x02000001@l
142 stw r3, 0x54(r4) /* Boot enable, CS0 disable */
143 #endif /* CONFIG_SYS_LOWBOOT */
145 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
146 lis r3, CONFIG_SYS_MBAR@h
147 ori r3, r3, CONFIG_SYS_MBAR@l
148 #if defined(CONFIG_MPC5200)
149 /* MBAR is mirrored into the MBAR SPR */
151 rlwinm r3, r3, 16, 16, 31
153 #if defined(CONFIG_MGT5100)
154 rlwinm r3, r3, 17, 15, 31
156 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
158 #endif /* CONFIG_SYS_DEFAULT_MBAR */
160 /* Initialise the MPC5xxx processor core */
161 /*--------------------------------------------------------------*/
165 /* initialize some things that are hard to access from C */
166 /*--------------------------------------------------------------*/
168 /* set up stack in on-chip SRAM */
169 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
170 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
171 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
172 li r0, 0 /* Make room for stack frame header and */
173 stwu r0, -4(r1) /* clear final stack frame so that */
174 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
176 /* let the C-code set up the rest */
178 /* Be careful to keep code relocatable ! */
179 /*--------------------------------------------------------------*/
181 GET_GOT /* initialize GOT access */
184 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
188 bl board_init_f /* run 1st part of board init code (in Flash)*/
194 .globl _start_of_vectors
198 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
200 /* Data Storage exception. */
201 STD_EXCEPTION(0x300, DataStorage, UnknownException)
203 /* Instruction Storage exception. */
204 STD_EXCEPTION(0x400, InstStorage, UnknownException)
206 /* External Interrupt exception. */
207 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
209 /* Alignment exception. */
212 EXCEPTION_PROLOG(SRR0, SRR1)
217 addi r3,r1,STACK_FRAME_OVERHEAD
219 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
220 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
221 lwz r6,GOT(transfer_to_handler)
225 .long AlignmentException - _start + EXC_OFF_SYS_RESET
226 .long int_return - _start + EXC_OFF_SYS_RESET
228 /* Program check exception */
231 EXCEPTION_PROLOG(SRR0, SRR1)
232 addi r3,r1,STACK_FRAME_OVERHEAD
234 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
235 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
236 lwz r6,GOT(transfer_to_handler)
240 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
241 .long int_return - _start + EXC_OFF_SYS_RESET
243 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
245 /* I guess we could implement decrementer, and may have
246 * to someday for timekeeping.
248 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
250 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
251 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
252 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
253 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
255 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
256 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
258 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
259 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
260 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
264 * This exception occurs when the program counter matches the
265 * Instruction Address Breakpoint Register (IABR).
267 * I want the cpu to halt if this occurs so I can hunt around
268 * with the debugger and look at things.
270 * When DEBUG is defined, both machine check enable (in the MSR)
271 * and checkstop reset enable (in the reset mode register) are
272 * turned off and so a checkstop condition will result in the cpu
275 * I force the cpu into a checkstop condition by putting an illegal
276 * instruction here (at least this is the theory).
278 * well - that didnt work, so just do an infinite loop!
282 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
284 STD_EXCEPTION(0x1400, SMI, UnknownException)
286 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
287 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
288 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
289 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
290 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
291 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
292 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
293 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
294 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
295 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
296 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
297 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
298 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
299 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
300 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
301 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
302 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
303 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
304 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
305 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
306 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
307 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
308 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
309 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
310 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
311 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
312 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
315 .globl _end_of_vectors
321 * This code finishes saving the registers to the exception frame
322 * and jumps to the appropriate handler for the exception.
323 * Register r21 is pointer into trap frame, r1 has new stack pointer.
325 .globl transfer_to_handler
336 andi. r24,r23,0x3f00 /* get vector offset */
340 lwz r24,0(r23) /* virtual address of handler */
341 lwz r23,4(r23) /* where to go when done */
346 rfi /* jump to handler, enable MMU */
349 mfmsr r28 /* Disable interrupts */
353 SYNC /* Some chip revs need this... */
368 lwz r2,_NIP(r1) /* Restore environment */
379 * This code initialises the MPC5xxx processor core
380 * (conforms to PowerPC 603e spec)
381 * Note: expects original MSR contents to be in r5.
387 /* Initialize machine status; enable machine check interrupt */
388 /*--------------------------------------------------------------*/
390 li r3, MSR_KERNEL /* Set ME and RI flags */
391 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
393 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
395 SYNC /* Some chip revs need this... */
398 mtspr SRR1, r3 /* Make SRR1 match MSR */
400 /* Initialize the Hardware Implementation-dependent Registers */
401 /* HID0 also contains cache control */
402 /*--------------------------------------------------------------*/
404 lis r3, CONFIG_SYS_HID0_INIT@h
405 ori r3, r3, CONFIG_SYS_HID0_INIT@l
409 lis r3, CONFIG_SYS_HID0_FINAL@h
410 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
414 /* clear all BAT's */
415 /*--------------------------------------------------------------*/
452 /* invalidate all tlb's */
454 /* From the 603e User Manual: "The 603e provides the ability to */
455 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
456 /* instruction invalidates the TLB entry indexed by the EA, and */
457 /* operates on both the instruction and data TLBs simultaneously*/
458 /* invalidating four TLB entries (both sets in each TLB). The */
459 /* index corresponds to bits 15-19 of the EA. To invalidate all */
460 /* entries within both TLBs, 32 tlbie instructions should be */
461 /* issued, incrementing this field by one each time." */
463 /* "Note that the tlbia instruction is not implemented on the */
466 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
467 /* incrementing by 0x1000 each time. The code below is sort of */
468 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
470 /*--------------------------------------------------------------*/
481 /*--------------------------------------------------------------*/
487 * Note: requires that all cache bits in
488 * HID0 are in the low half word.
495 ori r4, r4, HID0_ILOCK
497 ori r4, r3, HID0_ICFI
499 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
501 mtspr HID0, r3 /* clears invalidate */
504 .globl icache_disable
508 ori r4, r4, HID0_ICE|HID0_ILOCK
510 ori r4, r3, HID0_ICFI
512 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
514 mtspr HID0, r3 /* clears invalidate */
520 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
528 ori r4, r4, HID0_DLOCK
532 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
534 mtspr HID0, r3 /* clears invalidate */
537 .globl dcache_disable
541 ori r4, r4, HID0_DCE|HID0_DLOCK
545 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
547 mtspr HID0, r3 /* clears invalidate */
553 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
566 /*------------------------------------------------------------------------------*/
569 * void relocate_code (addr_sp, gd, addr_moni)
571 * This "function" does not return, instead it continues in RAM
572 * after relocating the monitor code.
576 * r5 = length in bytes
581 mr r1, r3 /* Set new stack pointer */
582 mr r9, r4 /* Save copy of Global Data pointer */
583 mr r10, r5 /* Save copy of Destination Address */
585 mr r3, r5 /* Destination Address */
586 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
587 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
588 lwz r5, GOT(__init_end)
590 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
595 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
601 /* First our own GOT */
603 /* then the one used by the C code */
613 beq cr1,4f /* In place copy is not necessary */
614 beq 7f /* Protect against 0 count */
633 * Now flush the cache: note that we must start from a cache aligned
634 * address. Otherwise we might miss one cache line.
638 beq 7f /* Always flush prefetch queue in any case */
641 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
642 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
650 sync /* Wait for all dcbst to complete on bus */
651 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
652 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
660 7: sync /* Wait for all icbi to complete on bus */
664 * We are done. Do not return, instead branch to second part of board
665 * initialization, now running from RAM.
668 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
675 * Relocation Function, r14 point to got2+0x8000
677 * Adjust got2 pointers, no need to check for 0, this code
678 * already puts a few entries in the table.
680 li r0,__got2_entries@sectoff@l
681 la r3,GOT(_GOT2_TABLE_)
682 lwz r11,GOT(_GOT2_TABLE_)
692 * Now adjust the fixups and the pointers to the fixups
693 * in case we need to move ourselves again.
695 2: li r0,__fixup_entries@sectoff@l
696 lwz r3,GOT(_FIXUP_TABLE_)
710 * Now clear BSS segment
712 lwz r3,GOT(__bss_start)
726 mr r3, r9 /* Global Data pointer */
727 mr r4, r10 /* Destination Address */
731 * Copy exception vector code to low memory
734 * r7: source address, r8: end address, r9: target address
739 lwz r8, GOT(_end_of_vectors)
741 li r9, 0x100 /* reset vector always at 0x100 */
744 bgelr /* return if r7>=r8 - just in case */
746 mflr r4 /* save link register */
756 * relocate `hdlr' and `int_return' entries
758 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
759 li r8, Alignment - _start + EXC_OFF_SYS_RESET
762 addi r7, r7, 0x100 /* next exception vector */
766 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
769 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
772 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
773 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
776 addi r7, r7, 0x100 /* next exception vector */
780 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
781 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
784 addi r7, r7, 0x100 /* next exception vector */
788 mfmsr r3 /* now that the vectors have */
789 lis r7, MSR_IP@h /* relocated into low memory */
790 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
791 andc r3, r3, r7 /* (if it was on) */
792 SYNC /* Some chip revs need this... */
796 mtlr r4 /* restore link register */
800 * Function: relocate entries for one exception vector
803 lwz r0, 0(r7) /* hdlr ... */
804 add r0, r0, r3 /* ... += dest_addr */
807 lwz r0, 4(r7) /* int_return ... */
808 add r0, r0, r3 /* ... += dest_addr */