2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #if defined(CONFIG_MGT5100)
28 #define START_REG(start) ((start) >> 15)
29 #define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
30 #elif defined(CONFIG_MPC5200)
31 #define START_REG(start) ((start) >> 16)
32 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
36 * Breath some life into the CPU...
38 * Set up the memory map,
39 * initialize a bunch of registers.
41 void cpu_init_f (void)
43 DECLARE_GLOBAL_DATA_PTR;
45 unsigned long addecr = (1 << 25); /* Boot_CS */
46 #if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
47 addecr |= (1 << 22); /* SDRAM enable */
49 /* Pointer is writable since we allocated a register for it */
50 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
52 /* Clear initial global data */
53 memset ((void *) gd, 0, sizeof (gd_t));
56 * Memory Controller: configure chip selects and enable them
58 #if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE)
59 *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START);
60 *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START,
63 #if defined(CFG_BOOTCS_CFG)
64 *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG;
67 #if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE)
68 *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START);
69 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE);
70 /* CS0 and BOOT_CS cannot be enabled at once. */
71 /* addecr |= (1 << 16); */
73 #if defined(CFG_CS0_CFG)
74 *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG;
77 #if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE)
78 *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START);
79 *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE);
82 #if defined(CFG_CS1_CFG)
83 *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG;
86 #if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE)
87 *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START);
88 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE);
91 #if defined(CFG_CS2_CFG)
92 *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG;
95 #if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE)
96 *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START);
97 *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE);
100 #if defined(CFG_CS3_CFG)
101 *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG;
104 #if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE)
105 *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START);
106 *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE);
109 #if defined(CFG_CS4_CFG)
110 *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG;
113 #if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE)
114 *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START);
115 *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE);
118 #if defined(CFG_CS5_CFG)
119 *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG;
122 #if defined(CONFIG_MPC5200)
124 #if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE)
125 *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START);
126 *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE);
129 #if defined(CFG_CS6_CFG)
130 *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG;
133 #if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
134 *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
135 *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
138 #if defined(CFG_CS7_CFG)
139 *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG;
142 #if defined(CFG_CS_BURST)
143 *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST;
145 #if defined(CFG_CS_DEADCYCLE)
146 *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE;
148 #endif /* CONFIG_MPC5200 */
150 /* Enable chip selects */
151 *(vu_long *)MPC5XXX_ADDECR = addecr;
152 *(vu_long *)MPC5XXX_CS_CTRL = (1 << 24);
154 /* Setup pin multiplexing */
155 #if defined(CFG_GPS_PORT_CONFIG)
156 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG;
161 * initialize higher level parts of CPU like time base and timers
163 int cpu_init_r (void)
165 /* mask all interrupts */
166 #if defined(CONFIG_MGT5100)
167 *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00;
168 #elif defined(CONFIG_MPC5200)
169 *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00;
171 *(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
172 *(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
174 #if defined(CONFIG_MPC5200)
175 /* enable timebase */
176 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
179 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5XXX_FEC)
180 /* load FEC microcode */