2 * (C) Copyright 2000 - 2009
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Based ont the MPC5200 PSC driver.
24 * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
28 * Minimal serial functions needed to use one of the PSC ports
29 * as serial console interface.
34 #include <asm/processor.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #if defined(CONFIG_PSC_CONSOLE)
40 static void fifo_init (volatile psc512x_t *psc)
42 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
44 /* reset Rx & Tx fifo slice */
45 out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
46 out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
48 /* disable Tx & Rx FIFO interrupts */
49 out_be32(&psc->rfintmask, 0);
50 out_be32(&psc->tfintmask, 0);
52 out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
53 out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
55 /* enable Tx & Rx FIFO slice */
56 out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
57 out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
59 out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
60 __asm__ volatile ("sync");
65 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
66 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
67 unsigned long baseclk;
72 /* set MR register to point to MR1 */
73 out_8(&psc->command, PSC_SEL_MODE_REG_1);
76 out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
78 /* choose the prescaler by 16 for the Tx/Rx clock generation */
79 out_be16(&psc->psc_clock_select, 0xdd00);
81 /* switch to UART mode */
82 out_be32(&psc->sicr, 0);
84 /* mode register points to mr1 */
85 /* configure parity, bit length and so on in mode register 1*/
86 out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
87 /* now, mode register points to mr2 */
88 out_8(&psc->mode, PSC_MODE_1_STOPBIT);
90 /* calculate dividor for setting PSC CTUR and CTLR registers */
91 baseclk = (gd->ips_clk + 8) / 16;
92 div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
94 out_8(&psc->ctur, (div >> 8) & 0xff);
96 out_8(&psc->ctlr, div & 0xff);
98 /* disable all interrupts */
99 out_be16(&psc->psc_imr, 0);
101 /* reset and enable Rx/Tx */
102 out_8(&psc->command, PSC_RST_RX);
103 out_8(&psc->command, PSC_RST_TX);
104 out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
109 void serial_putc (const char c)
111 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
112 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
117 /* Wait for last character to go. */
118 while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
124 void serial_putc_raw (const char c)
126 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
127 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
129 /* Wait for last character to go. */
130 while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
137 void serial_puts (const char *s)
144 int serial_getc (void)
146 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
147 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
149 /* Wait for a character to arrive. */
150 while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
153 return psc->rfdata_8;
156 int serial_tstc (void)
158 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
159 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
161 return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
164 void serial_setbrg (void)
166 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
167 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
168 unsigned long baseclk, div;
170 baseclk = (gd->ips_clk + 8) / 16;
171 div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
173 out_8(&psc->ctur, (div >> 8) & 0xFF);
174 out_8(&psc->ctlr, div & 0xff); /* set baudrate */
177 void serial_setrts(int s)
179 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
180 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
183 /* Assert RTS (become LOW) */
184 out_8(&psc->op1, 0x1);
187 /* Negate RTS (become HIGH) */
188 out_8(&psc->op0, 0x1);
192 int serial_getcts(void)
194 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
195 volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
197 return (in_8(&psc->ip) & 0x1) ? 0 : 1;
199 #endif /* CONFIG_PSC_CONSOLE */