2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * Copyright (C) 2007-2009 DENX Software Engineering
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Derived from the MPC83xx code.
30 #include <asm/processor.h>
32 DECLARE_GLOBAL_DATA_PTR;
35 * Set up the memory map, initialize registers,
37 void cpu_init_f (volatile immap_t * im)
41 /* Pointer is writable since we allocated a register for it */
42 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
44 /* Clear initial global data */
45 memset ((void *) gd, 0, sizeof (gd_t));
47 /* system performance tweaking */
49 #ifdef CONFIG_SYS_ACR_PIPE_DEP
50 /* Arbiter pipeline depth */
51 out_be32(&im->arbiter.acr,
52 (im->arbiter.acr & ~ACR_PIPE_DEP) |
53 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
57 #ifdef CONFIG_SYS_ACR_RPTCNT
58 /* Arbiter repeat count */
59 out_be32(im->arbiter.acr,
60 (im->arbiter.acr & ~(ACR_RPTCNT)) |
61 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
65 /* RSR - Reset Status Register - clear all status */
66 gd->reset_status = im->reset.rsr;
67 out_be32(&im->reset.rsr, ~RSR_RES);
70 * RMR - Reset Mode Register - enable checkstop reset
72 out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
74 /* Set IPS-CSB divider: IPS = 1/2 CSB */
75 ips_div = in_be32(&im->clk.scfr[0]);
76 ips_div &= ~(SCFR1_IPS_DIV_MASK);
77 ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
78 out_be32(&im->clk.scfr[0], ips_div);
81 * Enable Time Base/Decrementer
83 * NOTICE: TB needs to be enabled as early as possible in order to
84 * have udelay() working; if not enabled, usually leads to a hang, like
85 * during FLASH chip identification etc.
87 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);