2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/regdef.h>
29 #include <asm/mipsregs.h>
30 #include <asm/addrspace.h>
31 #include <asm/cacheops.h>
36 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
37 * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
39 * Note that the above size is the maximum size of primary cache. U-Boot
40 * doesn't have L2 cache support for now.
42 #define MIPS_MAX_CACHE_SIZE 0x10000
44 #define INDEX_BASE KSEG0
46 .macro cache_op op addr
55 * cacheop macro to automate cache operations
56 * first some helpers...
58 #define _mincache(size, maxsize) \
59 bltu size,maxsize,9f ; \
63 #define _align(minaddr, maxaddr, linesize) \
65 subu AT,linesize,1 ; \
72 /* general operations */
75 #define doop2(op1, op2) \
80 /* specials for cache initialisation */
81 #define doop1lw(op1) \
83 #define doop1lw1(op1) \
87 #define doop121(op1,op2) \
94 #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
96 10: doop##tag##ops ; \
97 bne minaddr,maxaddr,10b ; \
98 add minaddr,linesize ; \
101 /* finally the cache operation macros */
102 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
105 _align(kva, n, cacheLineSize) ; \
106 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
109 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
110 _mincache(n, cacheSize); \
113 _align(kva, n, cacheLineSize) ; \
114 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
117 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
118 vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
120 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
121 icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
123 .macro f_fill64 dst, offset, val
124 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
125 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
126 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
127 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
128 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
129 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
130 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
131 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
133 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
134 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
135 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
136 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
137 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
138 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
139 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
140 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
145 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
147 LEAF(mips_init_icache)
150 /* clear tag to invalidate */
151 PTR_LI t0, INDEX_BASE
153 1: cache_op Index_Store_Tag_I t0
156 /* fill once, so data field parity is correct */
157 PTR_LI t0, INDEX_BASE
161 /* invalidate again - prudent but not strictly neccessary */
162 PTR_LI t0, INDEX_BASE
163 1: cache_op Index_Store_Tag_I t0
167 END(mips_init_icache)
170 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
172 LEAF(mips_init_dcache)
176 PTR_LI t0, INDEX_BASE
178 1: cache_op Index_Store_Tag_D t0
181 /* load from each line (in cached space) */
182 PTR_LI t0, INDEX_BASE
183 2: LONG_L zero, 0(t0)
187 PTR_LI t0, INDEX_BASE
188 1: cache_op Index_Store_Tag_D t0
192 END(mips_init_dcache)
194 /*******************************************************************************
196 * mips_cache_reset - low level initialisation of the primary caches
198 * This routine initialises the primary caches to ensure that they
199 * have good parity. It must be called by the ROM before any cached locations
200 * are used to prevent the possibility of data with bad parity being written to
202 * To initialise the instruction cache it is essential that a source of data
203 * with good parity is available. This routine
204 * will initialise an area of memory starting at location zero to be used as
205 * a source of parity.
210 NESTED(mips_cache_reset, 0, ra)
212 li t2, CFG_ICACHE_SIZE
213 li t3, CFG_DCACHE_SIZE
214 li t4, CFG_CACHELINE_SIZE
217 li v0, MIPS_MAX_CACHE_SIZE
220 * Now clear that much memory starting from zero.
225 f_fill64 a0, -64, zero
229 * The caches are probably in an indeterminate state,
230 * so we force good parity into them by doing an
231 * invalidate, load/fill, invalidate for each line.
235 * Assume bottom of RAM will generate good parity for the cache.
239 * Initialize the I-cache first,
243 PTR_LA t7, mips_init_icache
247 * then initialize D-cache.
251 PTR_LA t7, mips_init_dcache
255 END(mips_cache_reset)
257 /*******************************************************************************
259 * dcache_status - get cache status
261 * RETURNS: 0 - cache disabled; 1 - cache enabled
266 li t1, CONF_CM_UNCACHED
267 andi t0, t0, CONF_CM_CMASK
274 /*******************************************************************************
276 * dcache_disable - disable cache
285 ori t0, t0, CONF_CM_UNCACHED
290 /*******************************************************************************
292 * dcache_enable - enable cache
299 ori t0, CONF_CM_CMASK
300 xori t0, CONF_CM_CMASK
301 ori t0, CONF_CM_CACHABLE_NONCOHERENT
306 #ifdef CFG_INIT_RAM_LOCK_MIPS
307 /*******************************************************************************
309 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
314 #if defined(CONFIG_PURPLE)
315 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
317 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
319 .globl mips_cache_lock
322 li a1, K0BASE - CACHE_LOCK_SIZE
324 li a2, CACHE_LOCK_SIZE
325 li a3, CFG_CACHELINE_SIZE
327 icacheop(a0,a1,a2,a3,0x1d)
332 #endif /* CFG_INIT_RAM_LOCK_MIPS */