2 * Cache-handling routined for MIPS 4K CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/regdef.h>
29 #include <asm/mipsregs.h>
30 #include <asm/addrspace.h>
31 #include <asm/cacheops.h>
33 /* 16KB is the maximum size of instruction and data caches on
36 #define MIPS_MAX_CACHE_SIZE 0x4000
39 * cacheop macro to automate cache operations
40 * first some helpers...
42 #define _mincache(size, maxsize) \
43 bltu size,maxsize,9f ; \
47 #define _align(minaddr, maxaddr, linesize) \
49 subu AT,linesize,1 ; \
56 /* general operations */
59 #define doop2(op1, op2) \
64 /* specials for cache initialisation */
65 #define doop1lw(op1) \
67 #define doop1lw1(op1) \
71 #define doop121(op1,op2) \
78 #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
80 10: doop##tag##ops ; \
81 bne minaddr,maxaddr,10b ; \
82 add minaddr,linesize ; \
85 /* finally the cache operation macros */
86 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
89 _align(kva, n, cacheLineSize) ; \
90 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
93 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
94 _mincache(n, cacheSize); \
97 _align(kva, n, cacheLineSize) ; \
98 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
101 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
102 vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
104 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
105 icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
107 .macro f_fill64 dst, offset, val
108 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
109 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
110 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
111 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
112 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
113 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
114 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
115 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
117 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
118 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
119 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
120 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
121 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
122 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
123 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
124 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
128 /*******************************************************************************
130 * mips_cache_reset - low level initialisation of the primary caches
132 * This routine initialises the primary caches to ensure that they
133 * have good parity. It must be called by the ROM before any cached locations
134 * are used to prevent the possibility of data with bad parity being written to
136 * To initialise the instruction cache it is essential that a source of data
137 * with good parity is available. This routine
138 * will initialise an area of memory starting at location zero to be used as
139 * a source of parity.
144 NESTED(mips_cache_reset, 0, ra)
145 li t2, CFG_ICACHE_SIZE
146 li t3, CFG_DCACHE_SIZE
147 li t4, CFG_CACHELINE_SIZE
150 li v0, MIPS_MAX_CACHE_SIZE
153 * Now clear that much memory starting from zero.
158 f_fill64 a0, -64, zero
167 * The caches are probably in an indeterminate state,
168 * so we force good parity into them by doing an
169 * invalidate, load/fill, invalidate for each line.
172 /* Assume bottom of RAM will generate good parity for the cache.
176 move a2, t2 # icacheSize
177 move a3, t4 # icacheLineSize
179 icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
181 /* To support Orion/R4600, we initialise the data cache in 3 passes.
184 /* 1: initialise dcache tags.
188 move a2, t3 # dcacheSize
189 move a3, t5 # dcacheLineSize
191 icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
197 move a2, t3 # dcacheSize
198 move a3, t5 # dcacheLineSize
200 icacheopn(a0,a1,a2,a3,1lw,(dummy))
202 /* 3: clear dcache tags.
206 move a2, t3 # dcacheSize
207 move a3, t5 # dcacheLineSize
209 icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
212 END(mips_cache_reset)
214 /*******************************************************************************
216 * dcache_status - get cache status
218 * RETURNS: 0 - cache disabled; 1 - cache enabled
227 /*******************************************************************************
229 * dcache_disable - disable cache
238 ori t0, t0, CONF_CM_UNCACHED
243 #ifdef CFG_INIT_RAM_LOCK_MIPS
244 /*******************************************************************************
246 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
251 #if defined(CONFIG_PURPLE)
252 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
254 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
256 .globl mips_cache_lock
259 li a1, K0BASE - CACHE_LOCK_SIZE
261 li a2, CACHE_LOCK_SIZE
262 li a3, CFG_CACHELINE_SIZE
264 icacheop(a0,a1,a2,a3,0x1d)
269 #endif /* CFG_INIT_RAM_LOCK_MIPS */