2 * Cache-handling routined for MIPS 4K CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/regdef.h>
29 #include <asm/mipsregs.h>
30 #include <asm/addrspace.h>
31 #include <asm/cacheops.h>
35 /* 16KB is the maximum size of instruction and data caches on
38 #define MIPS_MAX_CACHE_SIZE 0x4000
40 #define INDEX_BASE KSEG0
42 .macro cache_op op addr
51 * cacheop macro to automate cache operations
52 * first some helpers...
54 #define _mincache(size, maxsize) \
55 bltu size,maxsize,9f ; \
59 #define _align(minaddr, maxaddr, linesize) \
61 subu AT,linesize,1 ; \
68 /* general operations */
71 #define doop2(op1, op2) \
76 /* specials for cache initialisation */
77 #define doop1lw(op1) \
79 #define doop1lw1(op1) \
83 #define doop121(op1,op2) \
90 #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
92 10: doop##tag##ops ; \
93 bne minaddr,maxaddr,10b ; \
94 add minaddr,linesize ; \
97 /* finally the cache operation macros */
98 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
101 _align(kva, n, cacheLineSize) ; \
102 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
105 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
106 _mincache(n, cacheSize); \
109 _align(kva, n, cacheLineSize) ; \
110 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
113 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
114 vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
116 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
117 icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
119 .macro f_fill64 dst, offset, val
120 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
121 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
122 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
123 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
124 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
125 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
126 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
127 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
129 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
130 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
131 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
132 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
133 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
134 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
135 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
136 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
141 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
143 LEAF(mips_init_icache)
146 /* clear tag to invalidate */
147 PTR_LI t0, INDEX_BASE
149 1: cache_op Index_Store_Tag_I t0
152 /* fill once, so data field parity is correct */
153 PTR_LI t0, INDEX_BASE
157 /* invalidate again - prudent but not strictly neccessary */
158 PTR_LI t0, INDEX_BASE
159 1: cache_op Index_Store_Tag_I t0
163 END(mips_init_icache)
166 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
168 LEAF(mips_init_dcache)
172 PTR_LI t0, INDEX_BASE
174 1: cache_op Index_Store_Tag_D t0
177 /* load from each line (in cached space) */
178 PTR_LI t0, INDEX_BASE
179 2: LONG_L zero, 0(t0)
183 PTR_LI t0, INDEX_BASE
184 1: cache_op Index_Store_Tag_D t0
188 END(mips_init_dcache)
190 /*******************************************************************************
192 * mips_cache_reset - low level initialisation of the primary caches
194 * This routine initialises the primary caches to ensure that they
195 * have good parity. It must be called by the ROM before any cached locations
196 * are used to prevent the possibility of data with bad parity being written to
198 * To initialise the instruction cache it is essential that a source of data
199 * with good parity is available. This routine
200 * will initialise an area of memory starting at location zero to be used as
201 * a source of parity.
206 NESTED(mips_cache_reset, 0, ra)
208 li t2, CFG_ICACHE_SIZE
209 li t3, CFG_DCACHE_SIZE
210 li t4, CFG_CACHELINE_SIZE
213 li v0, MIPS_MAX_CACHE_SIZE
216 * Now clear that much memory starting from zero.
221 f_fill64 a0, -64, zero
225 * The caches are probably in an indeterminate state,
226 * so we force good parity into them by doing an
227 * invalidate, load/fill, invalidate for each line.
231 * Assume bottom of RAM will generate good parity for the cache.
235 * Initialize the I-cache first,
242 * then initialize D-cache.
249 END(mips_cache_reset)
251 /*******************************************************************************
253 * dcache_status - get cache status
255 * RETURNS: 0 - cache disabled; 1 - cache enabled
264 /*******************************************************************************
266 * dcache_disable - disable cache
275 ori t0, t0, CONF_CM_UNCACHED
280 #ifdef CFG_INIT_RAM_LOCK_MIPS
281 /*******************************************************************************
283 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
288 #if defined(CONFIG_PURPLE)
289 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
291 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
293 .globl mips_cache_lock
296 li a1, K0BASE - CACHE_LOCK_SIZE
298 li a2, CACHE_LOCK_SIZE
299 li a3, CFG_CACHELINE_SIZE
301 icacheop(a0,a1,a2,a3,0x1d)
306 #endif /* CFG_INIT_RAM_LOCK_MIPS */