1 /* Only eth0 supported for now
4 * Thomas.Lange@corelatus.se
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #if defined(CFG_DISCOVER_PHY)
29 #error "PHY not supported yet"
30 /* We just assume that we are running 100FD for now */
31 /* We all use switches, right? ;-) */
34 /* I assume ethernet behaves like au1000 */
37 /* Base address differ between cpu:s */
38 #define ETH0_BASE AU1000_ETH0_BASE
39 #define MAC0_ENABLE AU1000_MAC0_ENABLE
42 #define ETH0_BASE AU1100_ETH0_BASE
43 #define MAC0_ENABLE AU1100_MAC0_ENABLE
46 #define ETH0_BASE AU1500_ETH0_BASE
47 #define MAC0_ENABLE AU1500_MAC0_ENABLE
50 #define ETH0_BASE AU1550_ETH0_BASE
51 #define MAC0_ENABLE AU1550_MAC0_ENABLE
53 #error "No valid cpu set"
64 #include <asm/au1x00.h>
66 #if defined(CONFIG_CMD_MII)
70 /* Ethernet Transmit and Receive Buffers */
71 #define DBUF_LENGTH 1520
72 #define PKT_MAXBUF_SIZE 1518
74 static char txbuf[DBUF_LENGTH];
79 /* 4 rx and 4 tx fifos */
85 u32 len; /* Only used for tx */
89 mac_fifo_t mac_fifo[NO_OF_FIFOS];
93 #if defined(CONFIG_CMD_MII)
94 int au1x00_miiphy_read(char *devname, unsigned char addr,
95 unsigned char reg, unsigned short * value)
97 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
98 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
100 unsigned int timedout = 20;
102 while (*mii_control_reg & MAC_MII_BUSY) {
104 if (--timedout == 0) {
105 printf("au1x00_eth: miiphy_read busy timeout!!\n");
110 mii_control = MAC_SET_MII_SELECT_REG(reg) |
111 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
113 *mii_control_reg = mii_control;
116 while (*mii_control_reg & MAC_MII_BUSY) {
118 if (--timedout == 0) {
119 printf("au1x00_eth: miiphy_read busy timeout!!\n");
123 *value = *mii_data_reg;
127 int au1x00_miiphy_write(char *devname, unsigned char addr,
128 unsigned char reg, unsigned short value)
130 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
131 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
133 unsigned int timedout = 20;
135 while (*mii_control_reg & MAC_MII_BUSY) {
137 if (--timedout == 0) {
138 printf("au1x00_eth: miiphy_write busy timeout!!\n");
143 mii_control = MAC_SET_MII_SELECT_REG(reg) |
144 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
146 *mii_data_reg = value;
147 *mii_control_reg = mii_control;
152 static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
153 volatile mac_fifo_t *fifo_tx =
154 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
158 /* tx fifo should always be idle */
159 fifo_tx[next_tx].len = length;
160 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
165 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
167 printf("TX timeout\n");
175 fifo_tx[next_tx].addr = 0;
176 fifo_tx[next_tx].len = 0;
179 res = fifo_tx[next_tx].status;
182 if(next_tx>=NO_OF_FIFOS){
188 static int au1x00_recv(struct eth_device* dev){
189 volatile mac_fifo_t *fifo_rx =
190 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
196 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
197 /* Nothing has been received */
201 status = fifo_rx[next_rx].status;
203 length = status&0x3FFF;
206 printf("Rx error 0x%x\n", status);
209 /* Pass the packet up to the protocol layers. */
210 NetReceive(NetRxPackets[next_rx], length - 4);
213 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
216 if(next_rx>=NO_OF_FIFOS){
221 return(0); /* Does anyone use this? */
224 static int au1x00_init(struct eth_device* dev, bd_t * bd){
226 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
227 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
228 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
229 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
230 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
231 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
232 volatile mac_fifo_t *fifo_tx =
233 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
234 volatile mac_fifo_t *fifo_rx =
235 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
238 next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
239 next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
241 /* We have to enable clocks before releasing reset */
242 *macen = MAC_EN_CLOCK_ENABLE;
246 /* We have to release reset before accessing registers */
247 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
248 MAC_EN_RESET1|MAC_EN_RESET2;
251 for(i=0;i<NO_OF_FIFOS;i++){
253 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
254 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
257 /* Put mac addr in little endian */
258 #define ea eth_get_dev()->enetaddr
259 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
260 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
261 (ea[1] << 8) | (ea[0] ) ;
266 /* Make sure the MAC buffer is in the correct endian mode */
267 #ifdef __LITTLE_ENDIAN
268 *mac_ctrl = MAC_FULL_DUPLEX;
270 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
272 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
274 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
280 static void au1x00_halt(struct eth_device* dev){
283 int au1x00_enet_initialize(bd_t *bis){
284 struct eth_device* dev;
286 if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
287 puts ("malloc failed\n");
291 memset(dev, 0, sizeof *dev);
293 sprintf(dev->name, "Au1X00 ethernet");
296 dev->init = au1x00_init;
297 dev->halt = au1x00_halt;
298 dev->send = au1x00_send;
299 dev->recv = au1x00_recv;
303 #if defined(CONFIG_CMD_MII)
304 miiphy_register(dev->name,
305 au1x00_miiphy_read, au1x00_miiphy_write);
311 #endif /* CONFIG_AU1X00 */