1 /* Only eth0 supported for now
4 * Thomas.Lange@corelatus.se
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_SYS_DISCOVER_PHY)
27 #error "PHY not supported yet"
28 /* We just assume that we are running 100FD for now */
29 /* We all use switches, right? ;-) */
32 /* I assume ethernet behaves like au1000 */
34 #ifdef CONFIG_SOC_AU1000
35 /* Base address differ between cpu:s */
36 #define ETH0_BASE AU1000_ETH0_BASE
37 #define MAC0_ENABLE AU1000_MAC0_ENABLE
39 #ifdef CONFIG_SOC_AU1100
40 #define ETH0_BASE AU1100_ETH0_BASE
41 #define MAC0_ENABLE AU1100_MAC0_ENABLE
43 #ifdef CONFIG_SOC_AU1500
44 #define ETH0_BASE AU1500_ETH0_BASE
45 #define MAC0_ENABLE AU1500_MAC0_ENABLE
47 #ifdef CONFIG_SOC_AU1550
48 #define ETH0_BASE AU1550_ETH0_BASE
49 #define MAC0_ENABLE AU1550_MAC0_ENABLE
51 #error "No valid cpu set"
62 #include <asm/au1x00.h>
64 #if defined(CONFIG_CMD_MII)
68 /* Ethernet Transmit and Receive Buffers */
69 #define DBUF_LENGTH 1520
70 #define PKT_MAXBUF_SIZE 1518
72 static char txbuf[DBUF_LENGTH];
77 /* 4 rx and 4 tx fifos */
83 u32 len; /* Only used for tx */
87 mac_fifo_t mac_fifo[NO_OF_FIFOS];
91 #if defined(CONFIG_CMD_MII)
92 int au1x00_miiphy_read(char *devname, unsigned char addr,
93 unsigned char reg, unsigned short * value)
95 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
96 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
98 unsigned int timedout = 20;
100 while (*mii_control_reg & MAC_MII_BUSY) {
102 if (--timedout == 0) {
103 printf("au1x00_eth: miiphy_read busy timeout!!\n");
108 mii_control = MAC_SET_MII_SELECT_REG(reg) |
109 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
111 *mii_control_reg = mii_control;
114 while (*mii_control_reg & MAC_MII_BUSY) {
116 if (--timedout == 0) {
117 printf("au1x00_eth: miiphy_read busy timeout!!\n");
121 *value = *mii_data_reg;
125 int au1x00_miiphy_write(char *devname, unsigned char addr,
126 unsigned char reg, unsigned short value)
128 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
129 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
131 unsigned int timedout = 20;
133 while (*mii_control_reg & MAC_MII_BUSY) {
135 if (--timedout == 0) {
136 printf("au1x00_eth: miiphy_write busy timeout!!\n");
141 mii_control = MAC_SET_MII_SELECT_REG(reg) |
142 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
144 *mii_data_reg = value;
145 *mii_control_reg = mii_control;
150 static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
151 volatile mac_fifo_t *fifo_tx =
152 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
156 /* tx fifo should always be idle */
157 fifo_tx[next_tx].len = length;
158 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
163 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
165 printf("TX timeout\n");
173 fifo_tx[next_tx].addr = 0;
174 fifo_tx[next_tx].len = 0;
177 res = fifo_tx[next_tx].status;
180 if(next_tx>=NO_OF_FIFOS){
186 static int au1x00_recv(struct eth_device* dev){
187 volatile mac_fifo_t *fifo_rx =
188 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
194 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
195 /* Nothing has been received */
199 status = fifo_rx[next_rx].status;
201 length = status&0x3FFF;
204 printf("Rx error 0x%x\n", status);
207 /* Pass the packet up to the protocol layers. */
208 NetReceive(NetRxPackets[next_rx], length - 4);
211 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
214 if(next_rx>=NO_OF_FIFOS){
219 return(0); /* Does anyone use this? */
222 static int au1x00_init(struct eth_device* dev, bd_t * bd){
224 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
225 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
226 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
227 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
228 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
229 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
230 volatile mac_fifo_t *fifo_tx =
231 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
232 volatile mac_fifo_t *fifo_rx =
233 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
236 next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
237 next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
239 /* We have to enable clocks before releasing reset */
240 *macen = MAC_EN_CLOCK_ENABLE;
244 /* We have to release reset before accessing registers */
245 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
246 MAC_EN_RESET1|MAC_EN_RESET2;
249 for(i=0;i<NO_OF_FIFOS;i++){
251 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
252 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
255 /* Put mac addr in little endian */
256 #define ea eth_get_dev()->enetaddr
257 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
258 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
259 (ea[1] << 8) | (ea[0] ) ;
264 /* Make sure the MAC buffer is in the correct endian mode */
265 #ifdef __LITTLE_ENDIAN
266 *mac_ctrl = MAC_FULL_DUPLEX;
268 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
270 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
272 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
278 static void au1x00_halt(struct eth_device* dev){
281 int au1x00_enet_initialize(bd_t *bis){
282 struct eth_device* dev;
284 if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
285 puts ("malloc failed\n");
289 memset(dev, 0, sizeof *dev);
291 sprintf(dev->name, "Au1X00 ethernet");
294 dev->init = au1x00_init;
295 dev->halt = au1x00_halt;
296 dev->send = au1x00_send;
297 dev->recv = au1x00_recv;
301 #if defined(CONFIG_CMD_MII)
302 miiphy_register(dev->name,
303 au1x00_miiphy_read, au1x00_miiphy_write);