2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <timestamp.h>
28 #ifndef CONFIG_IDENT_STRING
29 #define CONFIG_IDENT_STRING ""
32 /* last three long word reserved for cache status */
33 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
34 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
35 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
41 move.w #0x2700,%sr; /* disable intrs */ \
42 subl #60,%sp; /* space for 15 regs */ \
43 moveml %d0-%d7/%a0-%a6,%sp@;
46 moveml %sp@,%d0-%d7/%a0-%a6; \
47 addl #60,%sp; /* space for 15 regs */ \
50 #if defined(CONFIG_CF_SBF)
51 #define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
52 #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
58 * Vector table. This is used for initial platform startup.
59 * These vectors are to catch any un-intended traps.
62 #if defined(CONFIG_CF_SBF)
64 INITSP: .long 0 /* Initial SP */
65 INITPC: .long ASM_DRAMINIT /* Initial PC */
69 INITSP: .long 0 /* Initial SP */
70 INITPC: .long _START /* Initial PC */
74 vector02: .long _FAULT /* Access Error */
75 vector03: .long _FAULT /* Address Error */
76 vector04: .long _FAULT /* Illegal Instruction */
77 vector05: .long _FAULT /* Reserved */
78 vector06: .long _FAULT /* Reserved */
79 vector07: .long _FAULT /* Reserved */
80 vector08: .long _FAULT /* Privilege Violation */
81 vector09: .long _FAULT /* Trace */
82 vector0A: .long _FAULT /* Unimplemented A-Line */
83 vector0B: .long _FAULT /* Unimplemented F-Line */
84 vector0C: .long _FAULT /* Debug Interrupt */
85 vector0D: .long _FAULT /* Reserved */
86 vector0E: .long _FAULT /* Format Error */
87 vector0F: .long _FAULT /* Unitialized Int. */
91 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93 vector18: .long _FAULT /* Spurious Interrupt */
94 vector19: .long _FAULT /* Autovector Level 1 */
95 vector1A: .long _FAULT /* Autovector Level 2 */
96 vector1B: .long _FAULT /* Autovector Level 3 */
97 vector1C: .long _FAULT /* Autovector Level 4 */
98 vector1D: .long _FAULT /* Autovector Level 5 */
99 vector1E: .long _FAULT /* Autovector Level 6 */
100 vector1F: .long _FAULT /* Autovector Level 7 */
102 #if !defined(CONFIG_CF_SBF)
106 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
125 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
131 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
132 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
135 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
141 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
142 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
145 #if defined(CONFIG_CF_SBF)
146 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
148 .long 0x00000000 /* checksum, not yet implemented */
149 .long 0x00030000 /* image length */
150 .long TEXT_BASE /* image to be relocated at */
153 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
154 movec %d0, %RAMBAR1 /* init Rambar */
155 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
158 /* Must disable global address */
159 move.l #0xFC008000, %a1
160 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
161 move.l #0xFC008008, %a1
162 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
163 move.l #0xFC008004, %a1
164 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
167 * Dram Initialization
171 move.l #0xFC0A4074, %a1
172 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
175 /* SDRAM Chip 0 and 1 */
176 move.l #0xFC0B8110, %a1
177 move.l #0xFC0B8114, %a2
179 /* calculate the size */
181 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
182 #ifdef CONFIG_SYS_SDRAM_BASE1
192 /* SDRAM Chip 0 and 1 */
193 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
195 #ifdef CONFIG_SYS_SDRAM_BASE1
196 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
201 /* dram cfg1 and cfg2 */
202 move.l #0xFC0B8008, %a1
203 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
205 move.l #0xFC0B800C, %a2
206 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
209 move.l #0xFC0B8000, %a1 /* Mode */
210 move.l #0xFC0B8004, %a2 /* Ctrl */
212 #ifdef CONFIG_M54455EVB
214 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
218 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
220 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
231 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
234 /* Perform two refresh cycles */
235 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
241 #ifdef CONFIG_M54455EVB
242 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
244 #elif defined(CONFIG_M54451EVB)
246 move.l #(CONFIG_SYS_SDRAM_MODE), (%a2)
248 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a2)
258 move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
259 and.l #0x7FFFFFFF, %d0
260 #ifdef CONFIG_M54455EVB
261 or.l #0x10000c00, %d0
262 #elif defined(CONFIG_M54451EVB)
263 or.l #0x10000000, %d0
269 * DSPI Initialization
270 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
276 /* Enable pins for DSPI mode - chip-selects are enabled later */
277 move.l #0xFC0A4063, %a0
280 /* Configure DSPI module */
281 move.l #0xFC05C000, %a0
282 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
284 move.l #0xFC05C00C, %a0
285 move.l #0x3E000011, (%a0)
287 move.l #0xFC05C034, %a2 /* dtfr */
288 move.l #0xFC05C03B, %a3 /* drfr */
290 move.l #(ASM_SBF_IMG_HDR + 4), %a1
294 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
295 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
297 move.l #0xFC05C02C, %a1 /* dspi status */
299 /* Issue commands and address */
300 move.l #0x8002000B, %d2 /* Fast Read Cmd */
301 jsr asm_dspi_wr_status
302 jsr asm_dspi_rd_status
304 move.l #0x80020000, %d2 /* Address byte 2 */
305 jsr asm_dspi_wr_status
306 jsr asm_dspi_rd_status
308 move.l #0x80020000, %d2 /* Address byte 1 */
309 jsr asm_dspi_wr_status
310 jsr asm_dspi_rd_status
312 move.l #0x80020000, %d2 /* Address byte 0 */
313 jsr asm_dspi_wr_status
314 jsr asm_dspi_rd_status
316 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
317 jsr asm_dspi_wr_status
318 jsr asm_dspi_rd_status
320 /* Transfer serial boot header to sram */
322 move.l #0x80020000, %d2
323 jsr asm_dspi_wr_status
324 jsr asm_dspi_rd_status
326 move.b %d1, (%a0) /* read, copy to dst */
328 add.l #1, %a0 /* inc dst by 1 */
329 sub.l #1, %d4 /* dec cnt by 1 */
330 bne asm_dspi_rd_loop1
332 /* Transfer u-boot from serial flash to memory */
334 move.l #0x80020000, %d2
335 jsr asm_dspi_wr_status
336 jsr asm_dspi_rd_status
338 move.b %d1, (%a4) /* read, copy to dst */
340 add.l #1, %a4 /* inc dst by 1 */
341 sub.l #1, %d5 /* dec cnt by 1 */
342 bne asm_dspi_rd_loop2
344 move.l #0x00020000, %d2 /* Terminate */
345 jsr asm_dspi_wr_status
346 jsr asm_dspi_rd_status
348 /* jump to memory and execute */
349 move.l #(TEXT_BASE + 0x400), %a0
353 move.l (%a1), %d0 /* status */
354 and.l #0x0000F000, %d0
355 cmp.l #0x00003000, %d0
356 bgt asm_dspi_wr_status
362 move.l (%a1), %d0 /* status */
363 and.l #0x000000F0, %d0
366 beq asm_dspi_rd_status
370 #endif /* CONFIG_CF_SBF */
378 move.w #0x2700,%sr /* Mask off Interrupt */
380 /* Set vector base register at the beginning of the Flash */
381 #if defined(CONFIG_CF_SBF)
382 move.l #TEXT_BASE, %d0
385 move.l #CONFIG_SYS_FLASH_BASE, %d0
388 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
392 /* initialize general use internal ram */
394 move.l #(CACR_STATUS), %a1 /* CACR */
395 move.l #(ICACHE_STATUS), %a2 /* icache */
396 move.l #(DCACHE_STATUS), %a3 /* dcache */
401 /* invalidate and disable cache */
402 move.l #0x01004100, %d0 /* Invalidate cache cmd */
403 movec %d0, %CACR /* Invalidate cache */
410 /* set stackpointer to end of internal ram to get some stackspace for
412 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
415 move.l #__got_start, %a5 /* put relocation table address to a5 */
417 bsr cpu_init_f /* run low-level CPU init code (from flash) */
418 bsr board_init_f /* run low-level board init code (from flash) */
420 /* board_init_f() does not return */
422 /*------------------------------------------------------------------------------*/
425 * void relocate_code (addr_sp, gd, addr_moni)
427 * This "function" does not return, instead it continues in RAM
428 * after relocating the monitor code.
432 * r5 = length in bytes
438 move.l 8(%a6), %sp /* set new stack pointer */
440 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
441 move.l 16(%a6), %a0 /* Save copy of Destination Address */
443 move.l #CONFIG_SYS_MONITOR_BASE, %a1
444 move.l #__init_end, %a2
447 /* copy the code to RAM */
449 move.l (%a1)+, (%a3)+
454 * We are done. Do not return, instead branch to second part of board
455 * initialization, now running from RAM.
458 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
465 * Now clear BSS segment
468 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
470 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
477 * fix got table in RAM
480 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
481 move.l %a1,%a5 /* * fix got pointer register a5 */
484 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
494 /* calculate relative jump to board_init_r in ram */
496 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
498 /* set parameters for board_init_r */
499 move.l %a0,-(%sp) /* dest_addr */
500 move.l %d0,-(%sp) /* gd */
503 /*------------------------------------------------------------------------------*/
525 /*------------------------------------------------------------------------------*/
526 /* cache functions */
529 move.l #(CACR_STATUS), %a1 /* read CACR Status */
532 move.l #0x00040100, %d0 /* Invalidate icache */
535 move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
538 move.l #0x04088020, %d0 /* Enable bcache and icache */
541 move.l #(ICACHE_STATUS), %a1
546 .globl icache_disable
548 move.l #(CACR_STATUS), %a1 /* read CACR Status */
551 move.l #0xFFF77BFF, %d0
552 or.l #0x00040100, %d0 /* Setup cache mask */
553 movec %d0, %CACR /* Invalidate icache */
558 move.l #(ICACHE_STATUS), %a1
565 move.l #(ICACHE_STATUS), %a1
569 .globl icache_invalid
571 move.l #(CACR_STATUS), %a1 /* read CACR Status */
574 move.l #0x00040100, %d0 /* Invalidate icache */
575 movec %d0, %CACR /* Enable and invalidate cache */
580 move.l #(CACR_STATUS), %a1 /* read CACR Status */
583 move.l #0x01040100, %d0
584 movec %d0, %CACR /* Invalidate dcache */
586 move.l #0x80088020, %d0 /* Enable bcache and icache */
589 move.l #(DCACHE_STATUS), %a1
594 .globl dcache_disable
596 move.l #(CACR_STATUS), %a1 /* read CACR Status */
599 and.l #0x7FFFFFFF, %d0
600 or.l #0x01000000, %d0 /* Setup cache mask */
601 movec %d0, %CACR /* Disable dcache */
606 move.l #(DCACHE_STATUS), %a1
611 .globl dcache_invalid
613 move.l #(CACR_STATUS), %a1 /* read CACR Status */
616 move.l #0x81088020, %d0 /* Setup cache mask */
617 movec %d0, %CACR /* Enable and invalidate cache */
622 move.l #(DCACHE_STATUS), %a1
626 /*------------------------------------------------------------------------------*/
628 .globl version_string
630 .ascii U_BOOT_VERSION
631 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
632 .ascii CONFIG_IDENT_STRING, "\0"