3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include <asm/immap.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* PLL min/max specifications */
36 #define MAX_FVCO 500000 /* KHz */
37 #define MAX_FSYS 80000 /* KHz */
38 #define MIN_FSYS 58333 /* KHz */
40 #ifdef CONFIG_MCF5301x
41 #define FREF 20000 /* KHz */
42 #define MAX_MFD 63 /* Multiplier */
43 #define MIN_MFD 0 /* Multiplier */
46 /* Low Power Divider specifications */
47 #define MIN_LPD (0) /* Divider (not encoded) */
48 #define MAX_LPD (15) /* Divider (not encoded) */
49 #define DEFAULT_LPD (0) /* Divider (not encoded) */
53 #define FREF 16000 /* KHz */
54 #define MAX_MFD 135 /* Multiplier */
55 #define MIN_MFD 88 /* Multiplier */
57 /* Low Power Divider specifications */
58 #define MIN_LPD (1 << 0) /* Divider (not encoded) */
59 #define MAX_LPD (1 << 15) /* Divider (not encoded) */
60 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
63 #define BUSDIV 6 /* Divider */
65 /* Get the value of the current system clock */
66 int get_sys_clock(void)
68 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
69 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
72 /* Test to see if device is in LIMP mode */
73 if (ccm->misccr & CCM_MISCCR_LIMP) {
74 divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
75 #ifdef CONFIG_MCF5301x
76 return (FREF / (3 * (1 << divider)));
79 return (FREF / (2 << divider));
82 #ifdef CONFIG_MCF5301x
83 u32 pfdr = (pll->pcr & 0x3F) + 1;
84 u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
85 u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
87 return (((FREF * pfdr) / refdiv) / busdiv);
90 return ((FREF * pll->pfdr) / (BUSDIV * 4));
96 * Initialize the Low Power Divider circuit
99 * div Desired system frequency divider
102 * The resulting output system frequency
104 int clock_limp(int div)
106 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
109 /* Check bounds of divider */
115 /* Save of the current value of the SSIDIV so we don't overwrite the value */
116 temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
118 /* Apply the divider to the system clock */
119 ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
121 ccm->misccr |= CCM_MISCCR_LIMP;
123 return (FREF / (3 * (1 << div)));
126 /* Exit low power LIMP mode */
127 int clock_exit_limp(void)
129 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
133 ccm->misccr &= (~CCM_MISCCR_LIMP);
135 /* Wait for PLL to lock */
136 while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
138 fout = get_sys_clock();
143 /* Initialize the PLL
146 * fref PLL reference clock frequency in KHz
147 * fsys Desired PLL output frequency in KHz
148 * flags Operating parameters
151 * The resulting output system frequency
153 int clock_pll(int fsys, int flags)
155 #ifdef CONFIG_MCF532x
156 volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
158 volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
159 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
160 int fref, temp, fout, mfd;
166 /* Return current PLL output */
167 #ifdef CONFIG_MCF5301x
168 u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
169 mfd = (pll->pcr & 0x3F) + 1;
171 return (fref * mfd) / busdiv;
173 #ifdef CONFIG_MCF532x
176 return (fref * mfd / (BUSDIV * 4));
180 /* Check bounds of requested system clock */
188 * Multiplying by 100 when calculating the temp value,
189 * and then dividing by 100 to calculate the mfd allows
190 * for exact values without needing to include floating
193 temp = (100 * fsys) / fref;
194 #ifdef CONFIG_MCF5301x
195 mfd = (BUSDIV * temp) / 100;
197 /* Determine the output frequency for selected values */
198 fout = ((fref * mfd) / BUSDIV);
200 #ifdef CONFIG_MCF532x
201 mfd = (4 * BUSDIV * temp) / 100;
203 /* Determine the output frequency for selected values */
204 fout = ((fref * mfd) / (BUSDIV * 4));
208 * Check to see if the SDRAM has already been initialized.
209 * If it has then the SDRAM needs to be put into self refresh
210 * mode before reprogramming the PLL.
212 if (sdram->ctrl & SDRAMC_SDCR_REF)
213 sdram->ctrl &= ~SDRAMC_SDCR_CKE;
216 * Initialize the PLL to generate the new system clock frequency.
217 * The device must be put into LIMP mode to reprogram the PLL.
220 /* Enter LIMP mode */
221 clock_limp(DEFAULT_LPD);
223 #ifdef CONFIG_MCF5301x
225 PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
226 PLL_PDR_OUTDIV2(BUSDIV - 1) |
227 PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
228 PLL_PDR_OUTDIV4(USBDIV - 1);
230 pll->pcr &= PLL_PCR_FBDIV_MASK;
231 pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
233 #ifdef CONFIG_MCF532x
234 /* Reprogram PLL for desired fsys */
235 pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
243 /* Return the SDRAM to normal operation if it is in use. */
244 if (sdram->ctrl & SDRAMC_SDCR_REF)
245 sdram->ctrl |= SDRAMC_SDCR_CKE;
247 #ifdef CONFIG_MCF532x
249 * software workaround for SDRAM opeartion after exiting LIMP
252 *sdram_workaround = CONFIG_SYS_SDRAM_BASE;
255 /* wait for DQS logic to relock */
256 for (i = 0; i < 0x200; i++) ;
261 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
264 gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
265 gd->cpu_clk = (gd->bus_clk * 3);
267 #ifdef CONFIG_FSL_I2C
268 gd->i2c1_clk = gd->bus_clk;