3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include <asm/immap.h>
33 /* PLL min/max specifications */
34 #define MAX_FVCO 500000 /* KHz */
35 #define MAX_FSYS 80000 /* KHz */
36 #define MIN_FSYS 58333 /* KHz */
37 #define FREF 16000 /* KHz */
38 #define MAX_MFD 135 /* Multiplier */
39 #define MIN_MFD 88 /* Multiplier */
40 #define BUSDIV 6 /* Divider */
42 * Low Power Divider specifications
44 #define MIN_LPD (1 << 0) /* Divider (not encoded) */
45 #define MAX_LPD (1 << 15) /* Divider (not encoded) */
46 #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
49 * Get the value of the current system clock
55 * The current output system frequency
57 int get_sys_clock(void)
59 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
60 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
63 /* Test to see if device is in LIMP mode */
64 if (ccm->misccr & CCM_MISCCR_LIMP) {
65 divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
66 return (FREF / (2 << divider));
68 return ((FREF * pll->pfdr) / (BUSDIV * 4));
73 * Initialize the Low Power Divider circuit
76 * div Desired system frequency divider
79 * The resulting output system frequency
81 int clock_limp(int div)
83 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
86 /* Check bounds of divider */
92 /* Save of the current value of the SSIDIV so we don't overwrite the value */
93 temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
95 /* Apply the divider to the system clock */
96 ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
98 ccm->misccr |= CCM_MISCCR_LIMP;
100 return (FREF / (3 * (1 << div)));
104 * Exit low power LIMP mode
107 * div Desired system frequency divider
110 * The resulting output system frequency
112 int clock_exit_limp(void)
114 volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
118 ccm->misccr &= (~CCM_MISCCR_LIMP);
120 /* Wait for PLL to lock */
121 while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
123 fout = get_sys_clock();
128 /* Initialize the PLL
131 * fref PLL reference clock frequency in KHz
132 * fsys Desired PLL output frequency in KHz
133 * flags Operating parameters
136 * The resulting output system frequency
138 int clock_pll(int fsys, int flags)
140 volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
141 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
142 int fref, temp, fout, mfd;
148 /* Return current PLL output */
151 return (fref * mfd / (BUSDIV * 4));
154 /* Check bounds of requested system clock */
161 /* Multiplying by 100 when calculating the temp value,
162 and then dividing by 100 to calculate the mfd allows
163 for exact values without needing to include floating
165 temp = (100 * fsys) / fref;
166 mfd = (4 * BUSDIV * temp) / 100;
168 /* Determine the output frequency for selected values */
169 fout = ((fref * mfd) / (BUSDIV * 4));
172 * Check to see if the SDRAM has already been initialized.
173 * If it has then the SDRAM needs to be put into self refresh
174 * mode before reprogramming the PLL.
178 * Initialize the PLL to generate the new system clock frequency.
179 * The device must be put into LIMP mode to reprogram the PLL.
182 /* Enter LIMP mode */
183 clock_limp(DEFAULT_LPD);
185 /* Reprogram PLL for desired fsys */
186 pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
194 * Return the SDRAM to normal operation if it is in use.
197 /* software workaround for SDRAM opeartion after exiting LIMP mode errata */
198 *sdram_workaround = CFG_SDRAM_BASE;
200 /* wait for DQS logic to relock */
201 for (i = 0; i < 0x200; i++) ;
207 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
211 DECLARE_GLOBAL_DATA_PTR;
213 gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000;
214 gd->cpu_clk = (gd->bus_clk * 3);