3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap.h>
32 #if defined(CONFIG_CMD_NET)
38 #ifdef CONFIG_MCF5301x
41 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
42 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
43 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
44 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
46 /* watchdog is enabled by default - disable the watchdog */
47 #ifndef CONFIG_WATCHDOG
51 scm1->mpr = 0x77777777;
60 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
61 && defined(CONFIG_SYS_CS0_CTRL))
62 gpio->par_cs |= GPIO_PAR_CS0_CS0;
63 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
64 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
65 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
68 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
69 && defined(CONFIG_SYS_CS1_CTRL))
70 gpio->par_cs |= GPIO_PAR_CS1_CS1;
71 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
72 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
73 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
76 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
77 && defined(CONFIG_SYS_CS2_CTRL))
78 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
79 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
80 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
83 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
84 && defined(CONFIG_SYS_CS3_CTRL))
85 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
86 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
87 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
90 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
91 && defined(CONFIG_SYS_CS4_CTRL))
92 gpio->par_cs |= GPIO_PAR_CS4;
93 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
94 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
95 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
98 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
99 && defined(CONFIG_SYS_CS5_CTRL))
100 gpio->par_cs |= GPIO_PAR_CS5;
101 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
102 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
103 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
106 #ifdef CONFIG_FSL_I2C
107 gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
113 /* initialize higher level parts of CPU like timers */
117 volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
120 volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
121 volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
123 rtcex->gocu = CONFIG_SYS_RTC_CNT;
124 rtcex->gocl = CONFIG_SYS_RTC_SETUP;
128 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
129 ccm->misccr |= CCM_MISCCR_FECM;
131 ccm->misccr &= ~CCM_MISCCR_FECM;
137 void uart_port_conf(void)
139 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
142 switch (CONFIG_SYS_UART_PORT) {
144 gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
147 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
149 ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
151 (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
152 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
154 ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
156 (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
160 #ifdef CONFIG_SYS_UART2_PRI_GPIO
161 gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
162 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
164 ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
166 (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
167 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
169 ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
171 (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
177 #if defined(CONFIG_CMD_NET)
178 int fecpin_setclear(struct eth_device *dev, int setclear)
180 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
181 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
184 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
186 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
188 GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
191 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
193 GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
196 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
198 ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
199 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
202 ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
203 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
208 #endif /* CONFIG_CMD_NET */
209 #endif /* CONFIG_MCF5301x */
211 #ifdef CONFIG_MCF532x
212 void cpu_init_f(void)
214 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
215 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
216 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
217 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
218 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
220 /* watchdog is enabled by default - disable the watchdog */
221 #ifndef CONFIG_WATCHDOG
225 scm1->mpr0 = 0x77777777;
235 /* Port configuration */
238 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
239 && defined(CONFIG_SYS_CS0_CTRL))
240 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
241 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
242 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
245 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
246 && defined(CONFIG_SYS_CS1_CTRL))
247 /* Latch chipselect */
248 gpio->par_cs |= GPIO_PAR_CS1;
249 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
250 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
251 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
254 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
255 && defined(CONFIG_SYS_CS2_CTRL))
256 gpio->par_cs |= GPIO_PAR_CS2;
257 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
258 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
259 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
262 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
263 && defined(CONFIG_SYS_CS3_CTRL))
264 gpio->par_cs |= GPIO_PAR_CS3;
265 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
266 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
267 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
270 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
271 && defined(CONFIG_SYS_CS4_CTRL))
272 gpio->par_cs |= GPIO_PAR_CS4;
273 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
274 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
275 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
278 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
279 && defined(CONFIG_SYS_CS5_CTRL))
280 gpio->par_cs |= GPIO_PAR_CS5;
281 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
282 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
283 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
286 #ifdef CONFIG_FSL_I2C
287 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
294 * initialize higher level parts of CPU like timers
301 void uart_port_conf(void)
303 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
306 switch (CONFIG_SYS_UART_PORT) {
308 gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
312 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
315 gpio->par_timer &= 0x0F;
316 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
321 #if defined(CONFIG_CMD_NET)
322 int fecpin_setclear(struct eth_device *dev, int setclear)
324 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
327 gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
329 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
331 gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
333 ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
338 #endif /* CONFIG_MCF532x */