3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap.h>
32 #if defined(CONFIG_CMD_NET)
38 #ifdef CONFIG_MCF5301x
41 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
42 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
43 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
45 /* watchdog is enabled by default - disable the watchdog */
46 #ifndef CONFIG_WATCHDOG
50 scm1->mpr = 0x77777777;
59 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
60 && defined(CONFIG_SYS_CS0_CTRL))
61 gpio->par_cs |= GPIO_PAR_CS0_CS0;
62 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
63 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
64 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
67 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
68 && defined(CONFIG_SYS_CS1_CTRL))
69 gpio->par_cs |= GPIO_PAR_CS1_CS1;
70 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
71 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
72 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
75 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
76 && defined(CONFIG_SYS_CS2_CTRL))
77 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
78 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
79 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
82 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
83 && defined(CONFIG_SYS_CS3_CTRL))
84 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
85 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
86 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
89 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
90 && defined(CONFIG_SYS_CS4_CTRL))
91 gpio->par_cs |= GPIO_PAR_CS4;
92 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
93 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
94 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
97 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
98 && defined(CONFIG_SYS_CS5_CTRL))
99 gpio->par_cs |= GPIO_PAR_CS5;
100 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
101 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
102 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
105 #ifdef CONFIG_FSL_I2C
106 gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
112 /* initialize higher level parts of CPU like timers */
116 volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
119 volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
120 volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
122 rtcex->gocu = CONFIG_SYS_RTC_CNT;
123 rtcex->gocl = CONFIG_SYS_RTC_SETUP;
127 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
128 ccm->misccr |= CCM_MISCCR_FECM;
130 ccm->misccr &= ~CCM_MISCCR_FECM;
136 void uart_port_conf(int port)
138 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
143 gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
144 gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
147 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
149 ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
150 GPIO_PAR_SIMP1H_VEN1_UNMASK);
152 (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
153 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
155 ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
157 (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
161 #ifdef CONFIG_SYS_UART2_PRI_GPIO
162 gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
163 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
165 ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
167 (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
168 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
170 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
172 (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
178 #if defined(CONFIG_CMD_NET)
179 int fecpin_setclear(struct eth_device *dev, int setclear)
181 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
182 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
185 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
187 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
189 GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
192 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
194 GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
197 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
199 ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
200 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
203 ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
204 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
209 #endif /* CONFIG_CMD_NET */
210 #endif /* CONFIG_MCF5301x */
212 #ifdef CONFIG_MCF532x
213 void cpu_init_f(void)
215 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
216 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
217 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
218 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
219 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
221 /* watchdog is enabled by default - disable the watchdog */
222 #ifndef CONFIG_WATCHDOG
226 scm1->mpr0 = 0x77777777;
236 /* Port configuration */
239 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
240 && defined(CONFIG_SYS_CS0_CTRL))
241 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
242 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
243 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
246 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
247 && defined(CONFIG_SYS_CS1_CTRL))
248 /* Latch chipselect */
249 gpio->par_cs |= GPIO_PAR_CS1;
250 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
251 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
252 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
255 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
256 && defined(CONFIG_SYS_CS2_CTRL))
257 gpio->par_cs |= GPIO_PAR_CS2;
258 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
259 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
260 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
263 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
264 && defined(CONFIG_SYS_CS3_CTRL))
265 gpio->par_cs |= GPIO_PAR_CS3;
266 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
267 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
268 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
271 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
272 && defined(CONFIG_SYS_CS4_CTRL))
273 gpio->par_cs |= GPIO_PAR_CS4;
274 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
275 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
276 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
279 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
280 && defined(CONFIG_SYS_CS5_CTRL))
281 gpio->par_cs |= GPIO_PAR_CS5;
282 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
283 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
284 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
287 #ifdef CONFIG_FSL_I2C
288 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
295 * initialize higher level parts of CPU like timers
302 void uart_port_conf(int port)
304 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
309 gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
310 gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
314 ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
316 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
319 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
320 gpio->par_timer &= 0x0F;
321 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
322 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
323 gpio->par_feci2c &= 0xFF00;
324 gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
325 #elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
326 gpio->par_ssi &= 0xF0FF;
327 gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
333 #if defined(CONFIG_CMD_NET)
334 int fecpin_setclear(struct eth_device *dev, int setclear)
336 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
339 gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
341 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
343 gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
345 ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
350 #endif /* CONFIG_MCF532x */