3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Arcturus Networks Inc. <www.arcturusnetworks.com>
11 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * Hayden Fraser (Hayden.Fraser@freescale.com)
16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/immap.h>
41 #if defined(CONFIG_CMD_NET)
48 /* Only 5272 Flexbus chipselect is different from the rest */
51 volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
53 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
54 && defined(CONFIG_SYS_CS0_CTRL))
55 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
56 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
57 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
59 #warning "Chip Select 0 are not initialized/used"
61 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
62 && defined(CONFIG_SYS_CS1_CTRL))
63 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
64 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
65 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
67 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
68 && defined(CONFIG_SYS_CS2_CTRL))
69 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
70 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
71 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
73 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
74 && defined(CONFIG_SYS_CS3_CTRL))
75 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
76 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
77 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
79 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
80 && defined(CONFIG_SYS_CS4_CTRL))
81 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
82 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
83 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
85 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
86 && defined(CONFIG_SYS_CS5_CTRL))
87 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
88 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
89 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
91 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
92 && defined(CONFIG_SYS_CS6_CTRL))
93 fbcs->csar6 = CONFIG_SYS_CS6_BASE;
94 fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
95 fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
97 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
98 && defined(CONFIG_SYS_CS7_CTRL))
99 fbcs->csar7 = CONFIG_SYS_CS7_BASE;
100 fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
101 fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
106 #if defined(CONFIG_M5208)
107 void cpu_init_f(void)
109 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
111 #ifndef CONFIG_WATCHDOG
112 volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
114 /* Disable the watchdog if we aren't using it */
118 scm1->mpr = 0x77777777;
126 /* FlexBus Chipselect */
132 /* initialize higher level parts of CPU like timers */
138 void uart_port_conf(void)
140 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
143 switch (CONFIG_SYS_UART_PORT) {
145 gpio->par_uart &= GPIO_PAR_UART0_MASK;
146 gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
149 gpio->par_uart &= GPIO_PAR_UART0_MASK;
150 gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
153 #ifdef CONFIG_SYS_UART2_PRI_GPIO
155 (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
157 (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
159 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
161 (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
163 (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
165 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
167 (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
169 (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
175 #if defined(CONFIG_CMD_NET)
176 int fecpin_setclear(struct eth_device *dev, int setclear)
178 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
182 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
184 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
187 (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
188 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
192 #endif /* CONFIG_CMD_NET */
193 #endif /* CONFIG_M5208 */
195 #if defined(CONFIG_M5253)
197 * Breath some life into the CPU...
199 * Set up the memory map,
200 * initialize a bunch of registers,
201 * initialize the UPM's
203 void cpu_init_f(void)
205 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
206 mbar_writeByte(MCFSIM_SYPCR, 0x00);
207 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
208 mbar_writeByte(MCFSIM_SWSR, 0x00);
209 mbar_writeByte(MCFSIM_SWDICR, 0x00);
210 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
211 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
212 mbar_writeByte(MCFSIM_I2CICR, 0x00);
213 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
214 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
215 mbar_writeByte(MCFSIM_ICR6, 0x00);
216 mbar_writeByte(MCFSIM_ICR7, 0x00);
217 mbar_writeByte(MCFSIM_ICR8, 0x00);
218 mbar_writeByte(MCFSIM_ICR9, 0x00);
219 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
221 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
222 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
223 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
225 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
227 /* FlexBus Chipselect */
230 #ifdef CONFIG_FSL_I2C
231 CONFIG_SYS_I2C_PINMUX_REG =
232 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
233 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
234 #ifdef CONFIG_SYS_I2C2_OFFSET
235 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
236 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
240 /* enable instruction cache now */
244 /*initialize higher level parts of CPU like timers */
250 void uart_port_conf(void)
253 switch (CONFIG_SYS_UART_PORT) {
262 #endif /* #if defined(CONFIG_M5253) */
264 #if defined(CONFIG_M5271)
265 void cpu_init_f(void)
267 #ifndef CONFIG_WATCHDOG
268 /* Disable the watchdog if we aren't using it */
269 mbar_writeShort(MCF_WTM_WCR, 0);
272 /* FlexBus Chipselect */
275 #ifdef CONFIG_SYS_MCF_SYNCR
276 /* Set clockspeed according to board header file */
277 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
279 /* Set clockspeed to 100MHz */
280 mbar_writeLong(MCF_FMPLL_SYNCR,
281 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
283 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
287 * initialize higher level parts of CPU like timers
294 void uart_port_conf(void)
297 switch (CONFIG_SYS_UART_PORT) {
299 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
300 MCF_GPIO_PAR_UART_U0RXD);
303 mbar_writeShort(MCF_GPIO_PAR_UART,
304 MCF_GPIO_PAR_UART_U1RXD_UART1 |
305 MCF_GPIO_PAR_UART_U1TXD_UART1);
308 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
313 #if defined(CONFIG_CMD_NET)
314 int fecpin_setclear(struct eth_device *dev, int setclear)
317 /* Enable Ethernet pins */
318 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
319 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
325 #endif /* CONFIG_CMD_NET */
328 #if defined(CONFIG_M5272)
330 * Breath some life into the CPU...
332 * Set up the memory map,
333 * initialize a bunch of registers,
334 * initialize the UPM's
336 void cpu_init_f(void)
338 /* if we come from RAM we assume the CPU is
339 * already initialized.
341 #ifndef CONFIG_MONITOR_IS_IN_RAM
342 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
343 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
344 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
346 sysctrl->sc_scr = CONFIG_SYS_SCR;
347 sysctrl->sc_spr = CONFIG_SYS_SPR;
350 gpio->gpio_pacnt = CONFIG_SYS_PACNT;
351 gpio->gpio_paddr = CONFIG_SYS_PADDR;
352 gpio->gpio_padat = CONFIG_SYS_PADAT;
353 gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
354 gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
355 gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
356 gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
358 /* Memory Controller: */
359 csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
360 csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
362 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
363 csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
364 csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
367 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
368 csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
369 csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
372 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
373 csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
374 csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
377 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
378 csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
379 csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
382 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
383 csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
384 csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
387 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
388 csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
389 csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
392 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
393 csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
394 csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
397 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
399 /* enable instruction cache now */
405 * initialize higher level parts of CPU like timers
412 void uart_port_conf(void)
414 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
417 switch (CONFIG_SYS_UART_PORT) {
419 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
420 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
423 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
424 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
429 #if defined(CONFIG_CMD_NET)
430 int fecpin_setclear(struct eth_device *dev, int setclear)
432 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
435 gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
436 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
437 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
438 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
443 #endif /* CONFIG_CMD_NET */
444 #endif /* #if defined(CONFIG_M5272) */
446 #if defined(CONFIG_M5275)
449 * Breathe some life into the CPU...
451 * Set up the memory map,
452 * initialize a bunch of registers,
453 * initialize the UPM's
455 void cpu_init_f(void)
458 * if we come from RAM we assume the CPU is
459 * already initialized.
462 #ifndef CONFIG_MONITOR_IS_IN_RAM
463 volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
464 volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
466 /* Kill watchdog so we can initialize the PLL */
469 /* FlexBus Chipselect */
471 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
473 #ifdef CONFIG_FSL_I2C
474 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
475 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
478 /* enable instruction cache now */
483 * initialize higher level parts of CPU like timers
490 void uart_port_conf(void)
492 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
495 switch (CONFIG_SYS_UART_PORT) {
497 gpio->par_uart |= UART0_ENABLE_MASK;
500 gpio->par_uart |= UART1_ENABLE_MASK;
503 gpio->par_uart |= UART2_ENABLE_MASK;
508 #if defined(CONFIG_CMD_NET)
509 int fecpin_setclear(struct eth_device *dev, int setclear)
511 struct fec_info_s *info = (struct fec_info_s *) dev->priv;
512 volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
515 /* Enable Ethernet pins */
516 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
517 gpio->par_feci2c |= 0x0F00;
518 gpio->par_fec0hl |= 0xC0;
520 gpio->par_feci2c |= 0x00A0;
521 gpio->par_fec1hl |= 0xC0;
524 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
525 gpio->par_feci2c &= ~0x0F00;
526 gpio->par_fec0hl &= ~0xC0;
528 gpio->par_feci2c &= ~0x00A0;
529 gpio->par_fec1hl &= ~0xC0;
535 #endif /* CONFIG_CMD_NET */
536 #endif /* #if defined(CONFIG_M5275) */
538 #if defined(CONFIG_M5282)
540 * Breath some life into the CPU...
542 * Set up the memory map,
543 * initialize a bunch of registers,
544 * initialize the UPM's
546 void cpu_init_f(void)
548 #ifndef CONFIG_WATCHDOG
549 /* disable watchdog if we aren't using it */
553 #ifndef CONFIG_MONITOR_IS_IN_RAM
556 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
557 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
558 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
560 MCFGPIO_PBCDPAR = 0xc0;
562 /* Set up the GPIO ports */
563 #ifdef CONFIG_SYS_PEPAR
564 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
566 #ifdef CONFIG_SYS_PFPAR
567 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
569 #ifdef CONFIG_SYS_PJPAR
570 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
572 #ifdef CONFIG_SYS_PSDPAR
573 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
575 #ifdef CONFIG_SYS_PASPAR
576 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
578 #ifdef CONFIG_SYS_PEHLPAR
579 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
581 #ifdef CONFIG_SYS_PQSPAR
582 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
584 #ifdef CONFIG_SYS_PTCPAR
585 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
587 #if defined(CONFIG_SYS_PORTTC)
588 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
590 #if defined(CONFIG_SYS_DDRTC)
591 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
593 #ifdef CONFIG_SYS_PTDPAR
594 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
596 #ifdef CONFIG_SYS_PUAPAR
597 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
600 #if defined(CONFIG_SYS_DDRD)
601 MCFGPIO_DDRD = CONFIG_SYS_DDRD;
603 #ifdef CONFIG_SYS_DDRUA
604 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
607 /* FlexBus Chipselect */
610 #endif /* CONFIG_MONITOR_IS_IN_RAM */
612 /* defer enabling cache until boot (see do_go) */
613 /* icache_enable(); */
617 * initialize higher level parts of CPU like timers
624 void uart_port_conf(void)
627 switch (CONFIG_SYS_UART_PORT) {
629 MCFGPIO_PUAPAR &= 0xFc;
630 MCFGPIO_PUAPAR |= 0x03;
633 MCFGPIO_PUAPAR &= 0xF3;
634 MCFGPIO_PUAPAR |= 0x0C;
637 MCFGPIO_PASPAR &= 0xFF0F;
638 MCFGPIO_PASPAR |= 0x00A0;
643 #if defined(CONFIG_CMD_NET)
644 int fecpin_setclear(struct eth_device *dev, int setclear)
647 MCFGPIO_PASPAR |= 0x0F00;
648 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
650 MCFGPIO_PASPAR &= 0xF0FF;
651 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
655 #endif /* CONFIG_CMD_NET */
658 #if defined(CONFIG_M5249)
660 * Breath some life into the CPU...
662 * Set up the memory map,
663 * initialize a bunch of registers,
664 * initialize the UPM's
666 void cpu_init_f(void)
669 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
670 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
671 * which is their primary function.
674 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
675 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
676 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
677 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
678 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
679 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
683 * You can verify these values by using dBug's 'ird'
684 * (Internal Register Display) command
688 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
689 mbar_writeByte(MCFSIM_SYPCR, 0x00);
690 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
691 mbar_writeByte(MCFSIM_SWSR, 0x00);
692 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
693 mbar_writeByte(MCFSIM_SWDICR, 0x00);
694 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
695 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
696 mbar_writeByte(MCFSIM_I2CICR, 0x00);
697 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
698 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
699 mbar_writeByte(MCFSIM_ICR6, 0x00);
700 mbar_writeByte(MCFSIM_ICR7, 0x00);
701 mbar_writeByte(MCFSIM_ICR8, 0x00);
702 mbar_writeByte(MCFSIM_ICR9, 0x00);
703 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
705 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
706 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
707 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
708 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
710 /* Setup interrupt priorities for gpio7 */
711 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
713 /* IDE Config registers */
714 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
715 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
717 /* FlexBus Chipselect */
720 /* enable instruction cache now */
725 * initialize higher level parts of CPU like timers
732 void uart_port_conf(void)
735 switch (CONFIG_SYS_UART_PORT) {
742 #endif /* #if defined(CONFIG_M5249) */