3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 * Hayden Fraser (Hayden.Fraser@freescale.com)
14 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/immap.h>
39 #if defined(CONFIG_M5253)
41 * Breath some life into the CPU...
43 * Set up the memory map,
44 * initialize a bunch of registers,
45 * initialize the UPM's
49 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
50 mbar_writeByte(MCFSIM_SYPCR, 0x00);
51 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
52 mbar_writeByte(MCFSIM_SWSR, 0x00);
53 mbar_writeByte(MCFSIM_SWDICR, 0x00);
54 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
55 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
56 mbar_writeByte(MCFSIM_I2CICR, 0x00);
57 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
58 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
59 mbar_writeByte(MCFSIM_ICR6, 0x00);
60 mbar_writeByte(MCFSIM_ICR7, 0x00);
61 mbar_writeByte(MCFSIM_ICR8, 0x00);
62 mbar_writeByte(MCFSIM_ICR9, 0x00);
63 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
65 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
66 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
67 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
69 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
72 * Setup chip selects...
75 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
76 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
77 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
79 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
80 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
81 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
83 /* enable instruction cache now */
87 /*initialize higher level parts of CPU like timers */
93 void uart_port_conf(void)
96 switch (CFG_UART_PORT) {
105 #endif /* #if defined(CONFIG_M5253) */
107 #if defined(CONFIG_M5271)
108 void cpu_init_f(void)
110 #ifndef CONFIG_WATCHDOG
111 /* Disable the watchdog if we aren't using it */
112 mbar_writeShort(MCF_WTM_WCR, 0);
115 /* Set clockspeed to 100MHz */
116 mbar_writeShort(MCF_FMPLL_SYNCR,
117 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
118 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
122 * initialize higher level parts of CPU like timers
129 void uart_port_conf(void)
132 switch (CFG_UART_PORT) {
134 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
135 MCF_GPIO_PAR_UART_U0RXD);
138 mbar_writeShort(MCF_GPIO_PAR_UART,
139 MCF_GPIO_PAR_UART_U1RXD_UART1 |
140 MCF_GPIO_PAR_UART_U1TXD_UART1);
143 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
149 #if defined(CONFIG_M5272)
151 * Breath some life into the CPU...
153 * Set up the memory map,
154 * initialize a bunch of registers,
155 * initialize the UPM's
157 void cpu_init_f(void)
159 /* if we come from RAM we assume the CPU is
160 * already initialized.
162 #ifndef CONFIG_MONITOR_IS_IN_RAM
163 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
164 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
165 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
167 sysctrl->sc_scr = CFG_SCR;
168 sysctrl->sc_spr = CFG_SPR;
171 gpio->gpio_pacnt = CFG_PACNT;
172 gpio->gpio_paddr = CFG_PADDR;
173 gpio->gpio_padat = CFG_PADAT;
174 gpio->gpio_pbcnt = CFG_PBCNT;
175 gpio->gpio_pbddr = CFG_PBDDR;
176 gpio->gpio_pbdat = CFG_PBDAT;
177 gpio->gpio_pdcnt = CFG_PDCNT;
179 /* Memory Controller: */
180 csctrl->cs_br0 = CFG_BR0_PRELIM;
181 csctrl->cs_or0 = CFG_OR0_PRELIM;
183 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
184 csctrl->cs_br1 = CFG_BR1_PRELIM;
185 csctrl->cs_or1 = CFG_OR1_PRELIM;
188 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
189 csctrl->cs_br2 = CFG_BR2_PRELIM;
190 csctrl->cs_or2 = CFG_OR2_PRELIM;
193 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
194 csctrl->cs_br3 = CFG_BR3_PRELIM;
195 csctrl->cs_or3 = CFG_OR3_PRELIM;
198 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
199 csctrl->cs_br4 = CFG_BR4_PRELIM;
200 csctrl->cs_or4 = CFG_OR4_PRELIM;
203 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
204 csctrl->cs_br5 = CFG_BR5_PRELIM;
205 csctrl->cs_or5 = CFG_OR5_PRELIM;
208 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
209 csctrl->cs_br6 = CFG_BR6_PRELIM;
210 csctrl->cs_or6 = CFG_OR6_PRELIM;
213 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
214 csctrl->cs_br7 = CFG_BR7_PRELIM;
215 csctrl->cs_or7 = CFG_OR7_PRELIM;
218 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
220 /* enable instruction cache now */
226 * initialize higher level parts of CPU like timers
233 void uart_port_conf(void)
235 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
238 switch (CFG_UART_PORT) {
240 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
241 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
244 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
245 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
249 #endif /* #if defined(CONFIG_M5272) */
251 #if defined(CONFIG_M5275)
254 * Breathe some life into the CPU...
256 * Set up the memory map,
257 * initialize a bunch of registers,
258 * initialize the UPM's
260 void cpu_init_f(void)
262 /* if we come from RAM we assume the CPU is
263 * already initialized.
266 #ifndef CONFIG_MONITOR_IS_IN_RAM
267 volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
268 volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
269 volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
271 /* Kill watchdog so we can initialize the PLL */
274 /* Memory Controller: */
276 csctrl_reg->ar0 = CFG_AR0_PRELIM;
277 csctrl_reg->cr0 = CFG_CR0_PRELIM;
278 csctrl_reg->mr0 = CFG_MR0_PRELIM;
280 #if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
281 csctrl_reg->ar1 = CFG_AR1_PRELIM;
282 csctrl_reg->cr1 = CFG_CR1_PRELIM;
283 csctrl_reg->mr1 = CFG_MR1_PRELIM;
286 #if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
287 csctrl_reg->ar2 = CFG_AR2_PRELIM;
288 csctrl_reg->cr2 = CFG_CR2_PRELIM;
289 csctrl_reg->mr2 = CFG_MR2_PRELIM;
292 #if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
293 csctrl_reg->ar3 = CFG_AR3_PRELIM;
294 csctrl_reg->cr3 = CFG_CR3_PRELIM;
295 csctrl_reg->mr3 = CFG_MR3_PRELIM;
298 #if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
299 csctrl_reg->ar4 = CFG_AR4_PRELIM;
300 csctrl_reg->cr4 = CFG_CR4_PRELIM;
301 csctrl_reg->mr4 = CFG_MR4_PRELIM;
304 #if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
305 csctrl_reg->ar5 = CFG_AR5_PRELIM;
306 csctrl_reg->cr5 = CFG_CR5_PRELIM;
307 csctrl_reg->mr5 = CFG_MR5_PRELIM;
310 #if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
311 csctrl_reg->ar6 = CFG_AR6_PRELIM;
312 csctrl_reg->cr6 = CFG_CR6_PRELIM;
313 csctrl_reg->mr6 = CFG_MR6_PRELIM;
316 #if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
317 csctrl_reg->ar7 = CFG_AR7_PRELIM;
318 csctrl_reg->cr7 = CFG_CR7_PRELIM;
319 csctrl_reg->mr7 = CFG_MR7_PRELIM;
322 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
324 #ifdef CONFIG_FSL_I2C
325 gpio_reg->par_feci2c = 0x000F;
328 /* enable instruction cache now */
333 * initialize higher level parts of CPU like timers
340 void uart_port_conf(void)
342 volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
345 switch (CFG_UART_PORT) {
347 gpio->par_uart |= UART0_ENABLE_MASK;
350 gpio->par_uart |= UART1_ENABLE_MASK;
353 gpio->par_uart |= UART2_ENABLE_MASK;
357 #endif /* #if defined(CONFIG_M5275) */
359 #if defined(CONFIG_M5282)
361 * Breath some life into the CPU...
363 * Set up the memory map,
364 * initialize a bunch of registers,
365 * initialize the UPM's
367 void cpu_init_f(void)
369 #ifndef CONFIG_WATCHDOG
370 /* disable watchdog if we aren't using it */
374 #ifndef CONFIG_MONITOR_IS_IN_RAM
377 MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
378 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
380 MCFGPIO_PBCDPAR = 0xc0;
382 /* Set up the GPIO ports */
384 MCFGPIO_PEPAR = CFG_PEPAR;
387 MCFGPIO_PFPAR = CFG_PFPAR;
390 MCFGPIO_PJPAR = CFG_PJPAR;
393 MCFGPIO_PSDPAR = CFG_PSDPAR;
396 MCFGPIO_PASPAR = CFG_PASPAR;
399 MCFGPIO_PEHLPAR = CFG_PEHLPAR;
402 MCFGPIO_PQSPAR = CFG_PQSPAR;
405 MCFGPIO_PTCPAR = CFG_PTCPAR;
408 MCFGPIO_PTDPAR = CFG_PTDPAR;
411 MCFGPIO_PUAPAR = CFG_PUAPAR;
415 MCFGPIO_DDRUA = CFG_DDRUA;
418 /* This is probably a bad place to setup chip selects, but everyone
421 #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
422 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
424 MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
426 #if (CFG_CS0_WIDTH == 8)
427 #define CFG_CS0_PS MCFCSM_CSCR_PS_8
428 #elif (CFG_CS0_WIDTH == 16)
429 #define CFG_CS0_PS MCFCSM_CSCR_PS_16
430 #elif (CFG_CS0_WIDTH == 32)
431 #define CFG_CS0_PS MCFCSM_CSCR_PS_32
433 #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
435 MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
436 | CFG_CS0_PS | MCFCSM_CSCR_AA;
438 #if (CFG_CS0_RO != 0)
439 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
440 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
442 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
445 #warning "Chip Select 0 are not initialized/used"
448 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
449 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
451 MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
453 #if (CFG_CS1_WIDTH == 8)
454 #define CFG_CS1_PS MCFCSM_CSCR_PS_8
455 #elif (CFG_CS1_WIDTH == 16)
456 #define CFG_CS1_PS MCFCSM_CSCR_PS_16
457 #elif (CFG_CS1_WIDTH == 32)
458 #define CFG_CS1_PS MCFCSM_CSCR_PS_32
460 #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
462 MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
463 | CFG_CS1_PS | MCFCSM_CSCR_AA;
465 #if (CFG_CS1_RO != 0)
466 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
467 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
469 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
473 #warning "Chip Select 1 are not initialized/used"
476 #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
477 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
479 MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
481 #if (CFG_CS2_WIDTH == 8)
482 #define CFG_CS2_PS MCFCSM_CSCR_PS_8
483 #elif (CFG_CS2_WIDTH == 16)
484 #define CFG_CS2_PS MCFCSM_CSCR_PS_16
485 #elif (CFG_CS2_WIDTH == 32)
486 #define CFG_CS2_PS MCFCSM_CSCR_PS_32
488 #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
490 MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
491 | CFG_CS2_PS | MCFCSM_CSCR_AA;
493 #if (CFG_CS2_RO != 0)
494 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
495 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
497 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
501 #warning "Chip Select 2 are not initialized/used"
504 #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
505 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
507 MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
509 #if (CFG_CS3_WIDTH == 8)
510 #define CFG_CS3_PS MCFCSM_CSCR_PS_8
511 #elif (CFG_CS3_WIDTH == 16)
512 #define CFG_CS3_PS MCFCSM_CSCR_PS_16
513 #elif (CFG_CS3_WIDTH == 32)
514 #define CFG_CS3_PS MCFCSM_CSCR_PS_32
516 #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
518 MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
519 | CFG_CS3_PS | MCFCSM_CSCR_AA;
521 #if (CFG_CS3_RO != 0)
522 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
523 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
525 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
529 #warning "Chip Select 3 are not initialized/used"
532 #endif /* CONFIG_MONITOR_IS_IN_RAM */
534 /* defer enabling cache until boot (see do_go) */
535 /* icache_enable(); */
539 * initialize higher level parts of CPU like timers
546 void uart_port_conf(void)
549 switch (CFG_UART_PORT) {
551 MCFGPIO_PUAPAR &= 0xFc;
552 MCFGPIO_PUAPAR |= 0x03;
555 MCFGPIO_PUAPAR &= 0xF3;
556 MCFGPIO_PUAPAR |= 0x0C;
559 MCFGPIO_PASPAR &= 0xFF0F;
560 MCFGPIO_PASPAR |= 0x00A0;
566 #if defined(CONFIG_M5249)
568 * Breath some life into the CPU...
570 * Set up the memory map,
571 * initialize a bunch of registers,
572 * initialize the UPM's
574 void cpu_init_f(void)
577 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
578 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
579 * which is their primary function.
582 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
583 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
584 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
585 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
586 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
587 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
591 * You can verify these values by using dBug's 'ird'
592 * (Internal Register Display) command
596 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
597 mbar_writeByte(MCFSIM_SYPCR, 0x00);
598 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
599 mbar_writeByte(MCFSIM_SWSR, 0x00);
600 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
601 mbar_writeByte(MCFSIM_SWDICR, 0x00);
602 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
603 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
604 mbar_writeByte(MCFSIM_I2CICR, 0x00);
605 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
606 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
607 mbar_writeByte(MCFSIM_ICR6, 0x00);
608 mbar_writeByte(MCFSIM_ICR7, 0x00);
609 mbar_writeByte(MCFSIM_ICR8, 0x00);
610 mbar_writeByte(MCFSIM_ICR9, 0x00);
611 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
613 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
614 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
615 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
616 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
618 /* Setup interrupt priorities for gpio7 */
619 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
621 /* IDE Config registers */
622 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
623 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
626 * Setup chip selects...
629 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
630 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
631 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
633 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
634 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
635 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
637 /* enable instruction cache now */
642 * initialize higher level parts of CPU like timers
649 void uart_port_conf(void)
652 switch (CFG_UART_PORT) {
659 #endif /* #if defined(CONFIG_M5249) */