3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 * Hayden Fraser (Hayden.Fraser@freescale.com)
14 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/immap.h>
39 #if defined(CONFIG_CMD_NET)
46 /* Only 5272 Flexbus chipselect is different from the rest */
49 volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
51 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
52 && defined(CONFIG_SYS_CS0_CTRL))
53 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
54 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
55 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
57 #warning "Chip Select 0 are not initialized/used"
59 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
60 && defined(CONFIG_SYS_CS1_CTRL))
61 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
62 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
63 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
65 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
66 && defined(CONFIG_SYS_CS2_CTRL))
67 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
68 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
69 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
71 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
72 && defined(CONFIG_SYS_CS3_CTRL))
73 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
74 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
75 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
77 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
78 && defined(CONFIG_SYS_CS4_CTRL))
79 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
80 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
81 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
83 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
84 && defined(CONFIG_SYS_CS5_CTRL))
85 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
86 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
87 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
89 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
90 && defined(CONFIG_SYS_CS6_CTRL))
91 fbcs->csar6 = CONFIG_SYS_CS6_BASE;
92 fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
93 fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
95 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
96 && defined(CONFIG_SYS_CS7_CTRL))
97 fbcs->csar7 = CONFIG_SYS_CS7_BASE;
98 fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
99 fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
104 #if defined(CONFIG_M5253)
106 * Breath some life into the CPU...
108 * Set up the memory map,
109 * initialize a bunch of registers,
110 * initialize the UPM's
112 void cpu_init_f(void)
114 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
115 mbar_writeByte(MCFSIM_SYPCR, 0x00);
116 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
117 mbar_writeByte(MCFSIM_SWSR, 0x00);
118 mbar_writeByte(MCFSIM_SWDICR, 0x00);
119 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
120 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
121 mbar_writeByte(MCFSIM_I2CICR, 0x00);
122 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
123 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
124 mbar_writeByte(MCFSIM_ICR6, 0x00);
125 mbar_writeByte(MCFSIM_ICR7, 0x00);
126 mbar_writeByte(MCFSIM_ICR8, 0x00);
127 mbar_writeByte(MCFSIM_ICR9, 0x00);
128 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
130 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
131 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
132 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
134 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
136 /* FlexBus Chipselect */
139 #ifdef CONFIG_FSL_I2C
140 CONFIG_SYS_I2C_PINMUX_REG =
141 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
142 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
143 #ifdef CONFIG_SYS_I2C2_OFFSET
144 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
145 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
149 /* enable instruction cache now */
153 /*initialize higher level parts of CPU like timers */
159 void uart_port_conf(void)
162 switch (CONFIG_SYS_UART_PORT) {
171 #endif /* #if defined(CONFIG_M5253) */
173 #if defined(CONFIG_M5271)
174 void cpu_init_f(void)
176 #ifndef CONFIG_WATCHDOG
177 /* Disable the watchdog if we aren't using it */
178 mbar_writeShort(MCF_WTM_WCR, 0);
181 /* FlexBus Chipselect */
184 #ifdef CONFIG_SYS_MCF_SYNCR
185 /* Set clockspeed according to board header file */
186 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
188 /* Set clockspeed to 100MHz */
189 mbar_writeLong(MCF_FMPLL_SYNCR,
190 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
192 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
196 * initialize higher level parts of CPU like timers
203 void uart_port_conf(void)
206 switch (CONFIG_SYS_UART_PORT) {
208 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
209 MCF_GPIO_PAR_UART_U0RXD);
212 mbar_writeShort(MCF_GPIO_PAR_UART,
213 MCF_GPIO_PAR_UART_U1RXD_UART1 |
214 MCF_GPIO_PAR_UART_U1TXD_UART1);
217 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
222 #if defined(CONFIG_CMD_NET)
223 int fecpin_setclear(struct eth_device *dev, int setclear)
226 /* Enable Ethernet pins */
227 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
228 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
234 #endif /* CONFIG_CMD_NET */
237 #if defined(CONFIG_M5272)
239 * Breath some life into the CPU...
241 * Set up the memory map,
242 * initialize a bunch of registers,
243 * initialize the UPM's
245 void cpu_init_f(void)
247 /* if we come from RAM we assume the CPU is
248 * already initialized.
250 #ifndef CONFIG_MONITOR_IS_IN_RAM
251 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
252 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
253 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
255 sysctrl->sc_scr = CONFIG_SYS_SCR;
256 sysctrl->sc_spr = CONFIG_SYS_SPR;
259 gpio->gpio_pacnt = CONFIG_SYS_PACNT;
260 gpio->gpio_paddr = CONFIG_SYS_PADDR;
261 gpio->gpio_padat = CONFIG_SYS_PADAT;
262 gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
263 gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
264 gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
265 gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
267 /* Memory Controller: */
268 csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
269 csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
271 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
272 csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
273 csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
276 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
277 csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
278 csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
281 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
282 csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
283 csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
286 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
287 csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
288 csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
291 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
292 csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
293 csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
296 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
297 csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
298 csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
301 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
302 csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
303 csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
306 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
308 /* enable instruction cache now */
314 * initialize higher level parts of CPU like timers
321 void uart_port_conf(void)
323 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
326 switch (CONFIG_SYS_UART_PORT) {
328 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
329 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
332 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
333 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
338 #if defined(CONFIG_CMD_NET)
339 int fecpin_setclear(struct eth_device *dev, int setclear)
341 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
344 gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
345 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
346 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
347 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
352 #endif /* CONFIG_CMD_NET */
353 #endif /* #if defined(CONFIG_M5272) */
355 #if defined(CONFIG_M5275)
358 * Breathe some life into the CPU...
360 * Set up the memory map,
361 * initialize a bunch of registers,
362 * initialize the UPM's
364 void cpu_init_f(void)
367 * if we come from RAM we assume the CPU is
368 * already initialized.
371 #ifndef CONFIG_MONITOR_IS_IN_RAM
372 volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
373 volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
375 /* Kill watchdog so we can initialize the PLL */
378 /* FlexBus Chipselect */
380 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
382 #ifdef CONFIG_FSL_I2C
383 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
384 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
387 /* enable instruction cache now */
392 * initialize higher level parts of CPU like timers
399 void uart_port_conf(void)
401 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
404 switch (CONFIG_SYS_UART_PORT) {
406 gpio->par_uart |= UART0_ENABLE_MASK;
409 gpio->par_uart |= UART1_ENABLE_MASK;
412 gpio->par_uart |= UART2_ENABLE_MASK;
417 #if defined(CONFIG_CMD_NET)
418 int fecpin_setclear(struct eth_device *dev, int setclear)
420 struct fec_info_s *info = (struct fec_info_s *) dev->priv;
421 volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
424 /* Enable Ethernet pins */
425 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
426 gpio->par_feci2c |= 0x0F00;
427 gpio->par_fec0hl |= 0xC0;
429 gpio->par_feci2c |= 0x00A0;
430 gpio->par_fec1hl |= 0xC0;
433 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
434 gpio->par_feci2c &= ~0x0F00;
435 gpio->par_fec0hl &= ~0xC0;
437 gpio->par_feci2c &= ~0x00A0;
438 gpio->par_fec1hl &= ~0xC0;
444 #endif /* CONFIG_CMD_NET */
445 #endif /* #if defined(CONFIG_M5275) */
447 #if defined(CONFIG_M5282)
449 * Breath some life into the CPU...
451 * Set up the memory map,
452 * initialize a bunch of registers,
453 * initialize the UPM's
455 void cpu_init_f(void)
457 #ifndef CONFIG_WATCHDOG
458 /* disable watchdog if we aren't using it */
462 #ifndef CONFIG_MONITOR_IS_IN_RAM
465 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
466 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
467 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
469 MCFGPIO_PBCDPAR = 0xc0;
471 /* Set up the GPIO ports */
472 #ifdef CONFIG_SYS_PEPAR
473 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
475 #ifdef CONFIG_SYS_PFPAR
476 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
478 #ifdef CONFIG_SYS_PJPAR
479 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
481 #ifdef CONFIG_SYS_PSDPAR
482 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
484 #ifdef CONFIG_SYS_PASPAR
485 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
487 #ifdef CONFIG_SYS_PEHLPAR
488 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
490 #ifdef CONFIG_SYS_PQSPAR
491 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
493 #ifdef CONFIG_SYS_PTCPAR
494 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
496 #ifdef CONFIG_SYS_PTDPAR
497 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
499 #ifdef CONFIG_SYS_PUAPAR
500 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
503 #ifdef CONFIG_SYS_DDRUA
504 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
507 /* FlexBus Chipselect */
510 #endif /* CONFIG_MONITOR_IS_IN_RAM */
512 /* defer enabling cache until boot (see do_go) */
513 /* icache_enable(); */
517 * initialize higher level parts of CPU like timers
524 void uart_port_conf(void)
527 switch (CONFIG_SYS_UART_PORT) {
529 MCFGPIO_PUAPAR &= 0xFc;
530 MCFGPIO_PUAPAR |= 0x03;
533 MCFGPIO_PUAPAR &= 0xF3;
534 MCFGPIO_PUAPAR |= 0x0C;
537 MCFGPIO_PASPAR &= 0xFF0F;
538 MCFGPIO_PASPAR |= 0x00A0;
543 #if defined(CONFIG_CMD_NET)
544 int fecpin_setclear(struct eth_device *dev, int setclear)
547 MCFGPIO_PASPAR |= 0x0F00;
548 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
550 MCFGPIO_PASPAR &= 0xF0FF;
551 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
555 #endif /* CONFIG_CMD_NET */
558 #if defined(CONFIG_M5249)
560 * Breath some life into the CPU...
562 * Set up the memory map,
563 * initialize a bunch of registers,
564 * initialize the UPM's
566 void cpu_init_f(void)
569 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
570 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
571 * which is their primary function.
574 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
575 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
576 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
577 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
578 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
579 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
583 * You can verify these values by using dBug's 'ird'
584 * (Internal Register Display) command
588 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
589 mbar_writeByte(MCFSIM_SYPCR, 0x00);
590 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
591 mbar_writeByte(MCFSIM_SWSR, 0x00);
592 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
593 mbar_writeByte(MCFSIM_SWDICR, 0x00);
594 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
595 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
596 mbar_writeByte(MCFSIM_I2CICR, 0x00);
597 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
598 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
599 mbar_writeByte(MCFSIM_ICR6, 0x00);
600 mbar_writeByte(MCFSIM_ICR7, 0x00);
601 mbar_writeByte(MCFSIM_ICR8, 0x00);
602 mbar_writeByte(MCFSIM_ICR9, 0x00);
603 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
605 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
606 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
607 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
608 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
610 /* Setup interrupt priorities for gpio7 */
611 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
613 /* IDE Config registers */
614 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
615 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
617 /* FlexBus Chipselect */
620 /* enable instruction cache now */
625 * initialize higher level parts of CPU like timers
632 void uart_port_conf(void)
635 switch (CONFIG_SYS_UART_PORT) {
642 #endif /* #if defined(CONFIG_M5249) */