3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/immap.h>
38 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
39 * determine which one we are running on, based on the Chip Identification
45 unsigned short cir; /* Chip Identification Register */
46 unsigned short pin; /* Part identification number */
47 unsigned char prn; /* Part revision number */
50 cir = mbar_readShort(MCF_CCM_CIR);
51 pin = cir >> MCF_CCM_CIR_PIN_LEN;
52 prn = cir & MCF_CCM_CIR_PRN_MASK;
55 case MCF_CCM_CIR_PIN_MCF5270:
58 case MCF_CCM_CIR_PIN_MCF5271:
67 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
68 cpu_model, prn, strmhz(buf, CFG_CLK));
70 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
71 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
72 pin, prn, strmhz(buf, CFG_CLK));
77 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
79 mbar_writeByte(MCF_RCM_RCR,
80 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
84 #if defined(CONFIG_WATCHDOG)
85 void watchdog_reset(void)
87 mbar_writeShort(MCF_WTM_WSR, 0x5555);
88 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
91 int watchdog_disable(void)
93 mbar_writeShort(MCF_WTM_WCR, 0);
97 int watchdog_init(void)
99 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
102 #endif /* #ifdef CONFIG_WATCHDOG */
107 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
109 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
114 /* enable watchdog, set timeout to 0 and wait */
118 /* we don't return! */
124 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
129 msk = (sysctrl->sc_dir > 28) & 0xf;
139 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
144 printf("Freescale MCF5272 %s\n", suf);
148 #if defined(CONFIG_WATCHDOG)
149 /* Called by macro WATCHDOG_RESET */
150 void watchdog_reset(void)
152 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
156 int watchdog_disable(void)
158 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
160 wdt->wdog_wcr = 0; /* reset watchdog counter */
161 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
162 wdt->wdog_wrrr = 0; /* disable watchdog timer */
164 puts("WATCHDOG:disabled\n");
168 int watchdog_init(void)
170 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
172 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
174 /* set timeout and enable watchdog */
176 ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
177 wdt->wdog_wcr = 0; /* reset watchdog counter */
179 puts("WATCHDOG:enabled\n");
182 #endif /* #ifdef CONFIG_WATCHDOG */
184 #endif /* #ifdef CONFIG_M5272 */
187 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
189 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
193 rcm->rcr = RCM_RCR_SOFTRST;
195 /* we don't return! */
203 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
204 strmhz(buf, CFG_CLK));
209 #if defined(CONFIG_WATCHDOG)
210 /* Called by macro WATCHDOG_RESET */
211 void watchdog_reset(void)
213 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
218 int watchdog_disable(void)
220 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
222 wdt->wsr = 0x5555; /* reset watchdog counter */
224 wdt->wcr = 0; /* disable watchdog timer */
226 puts("WATCHDOG:disabled\n");
230 int watchdog_init(void)
232 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
234 wdt->wcr = 0; /* disable watchdog */
236 /* set timeout and enable watchdog */
238 ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
239 wdt->wsr = 0x5555; /* reset watchdog counter */
242 puts("WATCHDOG:enabled\n");
245 #endif /* #ifdef CONFIG_WATCHDOG */
247 #endif /* #ifdef CONFIG_M5275 */
252 unsigned char resetsource = MCFRESET_RSR;
254 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
255 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
256 printf("Reset:%s%s%s%s%s%s%s\n",
257 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
258 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
259 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
260 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
261 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
262 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
263 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
267 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
269 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
279 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
280 strmhz(buf, CFG_CLK));
284 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
286 /* enable watchdog, set timeout to 0 and wait */
287 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
290 /* we don't return! */
300 unsigned char resetsource = mbar_readLong(SIM_RSR);
301 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
302 strmhz(buf, CFG_CLK));
304 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
305 printf("Reset:%s%s\n",
306 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
308 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
314 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
316 /* enable watchdog, set timeout to 0 and wait */
317 mbar_writeByte(SIM_SYPCR, 0xc0);
320 /* we don't return! */