3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/immap.h>
39 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
40 * determine which one we are running on, based on the Chip Identification
46 unsigned short cir; /* Chip Identification Register */
47 unsigned short pin; /* Part identification number */
48 unsigned char prn; /* Part revision number */
51 cir = mbar_readShort(MCF_CCM_CIR);
52 pin = cir >> MCF_CCM_CIR_PIN_LEN;
53 prn = cir & MCF_CCM_CIR_PRN_MASK;
56 case MCF_CCM_CIR_PIN_MCF5270:
59 case MCF_CCM_CIR_PIN_MCF5271:
68 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
69 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
71 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
72 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
73 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
78 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
80 mbar_writeByte(MCF_RCM_RCR,
81 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
85 #if defined(CONFIG_WATCHDOG)
86 void watchdog_reset(void)
88 mbar_writeShort(MCF_WTM_WSR, 0x5555);
89 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
92 int watchdog_disable(void)
94 mbar_writeShort(MCF_WTM_WCR, 0);
98 int watchdog_init(void)
100 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
103 #endif /* #ifdef CONFIG_WATCHDOG */
108 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
110 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
115 /* enable watchdog, set timeout to 0 and wait */
119 /* we don't return! */
125 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
130 msk = (sysctrl->sc_dir > 28) & 0xf;
140 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
145 printf("Freescale MCF5272 %s\n", suf);
149 #if defined(CONFIG_WATCHDOG)
150 /* Called by macro WATCHDOG_RESET */
151 void watchdog_reset(void)
153 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
157 int watchdog_disable(void)
159 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
161 wdt->wdog_wcr = 0; /* reset watchdog counter */
162 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
163 wdt->wdog_wrrr = 0; /* disable watchdog timer */
165 puts("WATCHDOG:disabled\n");
169 int watchdog_init(void)
171 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
173 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
175 /* set timeout and enable watchdog */
177 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
178 wdt->wdog_wcr = 0; /* reset watchdog counter */
180 puts("WATCHDOG:enabled\n");
183 #endif /* #ifdef CONFIG_WATCHDOG */
185 #endif /* #ifdef CONFIG_M5272 */
188 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
190 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
194 rcm->rcr = RCM_RCR_SOFTRST;
196 /* we don't return! */
204 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
205 strmhz(buf, CONFIG_SYS_CLK));
210 #if defined(CONFIG_WATCHDOG)
211 /* Called by macro WATCHDOG_RESET */
212 void watchdog_reset(void)
214 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
219 int watchdog_disable(void)
221 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
223 wdt->wsr = 0x5555; /* reset watchdog counter */
225 wdt->wcr = 0; /* disable watchdog timer */
227 puts("WATCHDOG:disabled\n");
231 int watchdog_init(void)
233 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
235 wdt->wcr = 0; /* disable watchdog */
237 /* set timeout and enable watchdog */
239 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
240 wdt->wsr = 0x5555; /* reset watchdog counter */
243 puts("WATCHDOG:enabled\n");
246 #endif /* #ifdef CONFIG_WATCHDOG */
248 #endif /* #ifdef CONFIG_M5275 */
253 unsigned char resetsource = MCFRESET_RSR;
255 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
256 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
257 printf("Reset:%s%s%s%s%s%s%s\n",
258 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
259 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
260 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
261 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
262 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
263 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
264 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
268 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
270 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
280 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
281 strmhz(buf, CONFIG_SYS_CLK));
285 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
287 /* enable watchdog, set timeout to 0 and wait */
288 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
291 /* we don't return! */
301 unsigned char resetsource = mbar_readLong(SIM_RSR);
302 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
303 strmhz(buf, CONFIG_SYS_CLK));
305 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
306 printf("Reset:%s%s\n",
307 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
309 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
315 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
317 /* enable watchdog, set timeout to 0 and wait */
318 mbar_writeByte(SIM_SYPCR, 0xc0);
321 /* we don't return! */
326 #if defined(CONFIG_MCFFEC)
327 /* Default initializations for MCFFEC controllers. To override,
328 * create a board-specific function called:
329 * int board_eth_init(bd_t *bis)
332 int cpu_eth_init(bd_t *bis)
334 return mcffec_initialize(bis);