3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
10 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/immap.h>
37 DECLARE_GLOBAL_DATA_PTR;
40 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
42 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
46 rcm->rcr = RCM_RCR_SOFTRST;
48 /* we don't return! */
54 char buf1[32], buf2[32];
56 printf("CPU: Freescale Coldfire MCF5208\n"
57 " CPU CLK %s MHz BUS CLK %s MHz\n",
58 strmhz(buf1, gd->cpu_clk),
59 strmhz(buf2, gd->bus_clk));
63 #if defined(CONFIG_WATCHDOG)
64 /* Called by macro WATCHDOG_RESET */
65 void watchdog_reset(void)
67 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
72 int watchdog_disable(void)
74 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
76 wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
79 wdt->cr = 0; /* disable watchdog timer */
81 puts("WATCHDOG:disabled\n");
85 int watchdog_init(void)
87 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
89 wdt->cr = 0; /* disable watchdog */
91 /* set timeout and enable watchdog */
93 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
94 wdt->sr = 0x5555; /* reset watchdog counter */
97 puts("WATCHDOG:enabled\n");
100 #endif /* #ifdef CONFIG_WATCHDOG */
101 #endif /* #ifdef CONFIG_M5208 */
105 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
106 * determine which one we are running on, based on the Chip Identification
112 unsigned short cir; /* Chip Identification Register */
113 unsigned short pin; /* Part identification number */
114 unsigned char prn; /* Part revision number */
117 cir = mbar_readShort(MCF_CCM_CIR);
118 pin = cir >> MCF_CCM_CIR_PIN_LEN;
119 prn = cir & MCF_CCM_CIR_PRN_MASK;
122 case MCF_CCM_CIR_PIN_MCF5270:
125 case MCF_CCM_CIR_PIN_MCF5271:
134 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
135 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
137 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
138 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
139 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
144 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
146 mbar_writeByte(MCF_RCM_RCR,
147 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
151 #if defined(CONFIG_WATCHDOG)
152 void watchdog_reset(void)
154 mbar_writeShort(MCF_WTM_WSR, 0x5555);
155 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
158 int watchdog_disable(void)
160 mbar_writeShort(MCF_WTM_WCR, 0);
164 int watchdog_init(void)
166 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
169 #endif /* #ifdef CONFIG_WATCHDOG */
174 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
176 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
181 /* enable watchdog, set timeout to 0 and wait */
185 /* we don't return! */
191 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
196 msk = (sysctrl->sc_dir > 28) & 0xf;
206 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
211 printf("Freescale MCF5272 %s\n", suf);
215 #if defined(CONFIG_WATCHDOG)
216 /* Called by macro WATCHDOG_RESET */
217 void watchdog_reset(void)
219 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
223 int watchdog_disable(void)
225 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
227 wdt->wdog_wcr = 0; /* reset watchdog counter */
228 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
229 wdt->wdog_wrrr = 0; /* disable watchdog timer */
231 puts("WATCHDOG:disabled\n");
235 int watchdog_init(void)
237 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
239 wdt->wdog_wirr = 0; /* disable watchdog interrupt */
241 /* set timeout and enable watchdog */
243 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
244 wdt->wdog_wcr = 0; /* reset watchdog counter */
246 puts("WATCHDOG:enabled\n");
249 #endif /* #ifdef CONFIG_WATCHDOG */
251 #endif /* #ifdef CONFIG_M5272 */
254 int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
256 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
260 rcm->rcr = RCM_RCR_SOFTRST;
262 /* we don't return! */
270 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
271 strmhz(buf, CONFIG_SYS_CLK));
276 #if defined(CONFIG_WATCHDOG)
277 /* Called by macro WATCHDOG_RESET */
278 void watchdog_reset(void)
280 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
285 int watchdog_disable(void)
287 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
289 wdt->wsr = 0x5555; /* reset watchdog counter */
291 wdt->wcr = 0; /* disable watchdog timer */
293 puts("WATCHDOG:disabled\n");
297 int watchdog_init(void)
299 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
301 wdt->wcr = 0; /* disable watchdog */
303 /* set timeout and enable watchdog */
305 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
306 wdt->wsr = 0x5555; /* reset watchdog counter */
309 puts("WATCHDOG:enabled\n");
312 #endif /* #ifdef CONFIG_WATCHDOG */
314 #endif /* #ifdef CONFIG_M5275 */
319 unsigned char resetsource = MCFRESET_RSR;
321 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
322 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
323 printf("Reset:%s%s%s%s%s%s%s\n",
324 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
325 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
326 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
327 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
328 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
329 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
330 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
334 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
336 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
346 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
347 strmhz(buf, CONFIG_SYS_CLK));
351 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
353 /* enable watchdog, set timeout to 0 and wait */
354 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
357 /* we don't return! */
367 unsigned char resetsource = mbar_readLong(SIM_RSR);
368 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
369 strmhz(buf, CONFIG_SYS_CLK));
371 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
372 printf("Reset:%s%s\n",
373 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
375 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
381 int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
383 /* enable watchdog, set timeout to 0 and wait */
384 mbar_writeByte(SIM_SYPCR, 0xc0);
387 /* we don't return! */
392 #if defined(CONFIG_MCFFEC)
393 /* Default initializations for MCFFEC controllers. To override,
394 * create a board-specific function called:
395 * int board_eth_init(bd_t *bis)
398 int cpu_eth_init(bd_t *bis)
400 return mcffec_initialize(bis);