1 /*-----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
25 | Function: This module has utilities for accessing the MII PHY through
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
35 | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
36 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
40 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
41 | <travis.sawyer@sandburst.com>
43 +-----------------------------------------------------------------------------*/
49 #include "IxEthAcc_p.h"
50 #include "IxEthAccMac_p.h"
51 #include "IxEthAccMii_p.h"
53 /***********************************************************/
54 /* Dump out to the screen PHY regs */
55 /***********************************************************/
57 void miiphy_dump (char *devname, unsigned char addr)
63 for (i = 0; i < 0x1A; i++) {
64 if (miiphy_read (devname, addr, i, &data)) {
65 printf ("read error for reg %lx\n", i);
68 printf ("Phy reg %lx ==> %4x\n", i, data);
70 /* jump to the next set of regs */
78 /***********************************************************/
79 /* (Re)start autonegotiation */
80 /***********************************************************/
81 int phy_setup_aneg (char *devname, unsigned char addr)
83 unsigned short ctl, adv;
85 /* Setup standard advertise */
86 miiphy_read (devname, addr, PHY_ANAR, &adv);
87 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
88 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
90 miiphy_write (devname, addr, PHY_ANAR, adv);
92 /* Start/Restart aneg */
93 miiphy_read (devname, addr, PHY_BMCR, &ctl);
94 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
95 miiphy_write (devname, addr, PHY_BMCR, ctl);
101 int npe_miiphy_read (char *devname, unsigned char addr,
102 unsigned char reg, unsigned short *value)
106 ixEthAccMiiReadRtn(addr, reg, &val);
113 int npe_miiphy_write (char *devname, unsigned char addr,
114 unsigned char reg, unsigned short value)
116 ixEthAccMiiWriteRtn(addr, reg, value);