3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /*------------------------------------------------------------------------------+ */
29 * This source code has been made available to you by IBM on an AS-IS
30 * basis. Anyone receiving this source is licensed under IBM
31 * copyrights to use it in any way he or she deems fit, including
32 * copying it, modifying it, compiling it, and redistributing it either
33 * with or without modifications. No license under IBM patents or
34 * patent applications is to be implied by the copyright license.
36 * Any user of this software should understand that IBM cannot provide
37 * technical support for this software and will not be responsible for
38 * any consequences resulting from the use of this software.
40 * Any person who transfers this source code or any derivative work
41 * must include the IBM copyright notice, this paragraph, and the
42 * preceding two paragraphs in the transferred software.
44 * COPYRIGHT I B M CORPORATION 1995
45 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
47 /*------------------------------------------------------------------------------- */
52 #include <asm/ibmpc.h>
54 #if CONFIG_SERIAL_SOFTWARE_FIFO
71 /*-----------------------------------------------------------------------------+
72 | Line Status Register.
73 +-----------------------------------------------------------------------------*/
74 #define asyncLSRDataReady1 0x01
75 #define asyncLSROverrunError1 0x02
76 #define asyncLSRParityError1 0x04
77 #define asyncLSRFramingError1 0x08
78 #define asyncLSRBreakInterrupt1 0x10
79 #define asyncLSRTxHoldEmpty1 0x20
80 #define asyncLSRTxShiftEmpty1 0x40
81 #define asyncLSRRxFifoError1 0x80
85 #if CONFIG_SERIAL_SOFTWARE_FIFO
86 /*-----------------------------------------------------------------------------+
88 +-----------------------------------------------------------------------------*/
96 volatile serial_buffer_t buf_info;
97 static int serial_buffer_active=0;
101 static int serial_div(int baudrate)
124 * Minimal serial functions needed to use one of the SMC ports
125 * as serial console interface.
128 int serial_init(void)
130 DECLARE_GLOBAL_DATA_PTR;
134 int bdiv = serial_div(gd->baudrate);
137 outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
138 outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */
139 outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
140 outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
141 outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */
142 outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */
143 val = inb(UART0_BASE + UART_LSR); /* clear line status */
144 val = inb(UART0_BASE + UART_RBR); /* read receive buffer */
145 outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */
146 outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */
152 void serial_setbrg(void)
154 DECLARE_GLOBAL_DATA_PTR;
158 bdiv = serial_div(gd->baudrate);
160 outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
161 outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */
162 outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */
163 outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */
167 void serial_putc(const char c)
174 /* check THRE bit, wait for transmiter available */
175 for (i = 1; i < 3500; i++) {
176 if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) {
181 outb(c, UART0_BASE + UART_THR); /* put character out */
185 void serial_puts(const char *s)
193 int serial_getc(void)
195 unsigned char status = 0;
197 #if CONFIG_SERIAL_SOFTWARE_FIFO
198 if (serial_buffer_active) {
199 return serial_buffered_getc();
204 #if defined(CONFIG_HW_WATCHDOG)
205 WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
206 #endif /* CONFIG_HW_WATCHDOG */
207 status = inb(UART0_BASE + UART_LSR);
208 if ((status & asyncLSRDataReady1) != 0x0) {
211 if ((status & ( asyncLSRFramingError1 |
212 asyncLSROverrunError1 |
213 asyncLSRParityError1 |
214 asyncLSRBreakInterrupt1 )) != 0) {
215 outb(asyncLSRFramingError1 |
216 asyncLSROverrunError1 |
217 asyncLSRParityError1 |
218 asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
221 return (0x000000ff & (int) inb (UART0_BASE));
225 int serial_tstc(void)
227 unsigned char status;
229 #if CONFIG_SERIAL_SOFTWARE_FIFO
230 if (serial_buffer_active) {
231 return serial_buffered_tstc();
235 status = inb(UART0_BASE + UART_LSR);
236 if ((status & asyncLSRDataReady1) != 0x0) {
239 if ((status & ( asyncLSRFramingError1 |
240 asyncLSROverrunError1 |
241 asyncLSRParityError1 |
242 asyncLSRBreakInterrupt1 )) != 0) {
243 outb(asyncLSRFramingError1 |
244 asyncLSROverrunError1 |
245 asyncLSRParityError1 |
246 asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR);
252 #if CONFIG_SERIAL_SOFTWARE_FIFO
254 void serial_isr(void *arg)
258 int rx_put = buf_info.rx_put;
260 if (buf_info.rx_get <= rx_put) {
261 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get);
263 space = buf_info.rx_get - rx_put;
266 while (inb(UART0_BASE + UART_LSR) & 1) {
269 buf_info.rx_buffer[rx_put++] = c;
272 if (rx_put == buf_info.rx_get) {
274 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
279 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
281 if (0 == buf_info.rx_get) {
288 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
289 /* Stop flow by setting RTS inactive */
290 outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02),
291 UART0_BASE + UART_MCR);
294 buf_info.rx_put = rx_put;
297 void serial_buffered_init(void)
299 serial_puts ("Switching to interrupt driven serial input mode.\n");
300 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
304 if (inb (UART0_BASE + UART_MSR) & 0x10) {
305 serial_puts ("Check CTS signal present on serial port: OK.\n");
308 serial_puts ("WARNING: CTS signal not present on serial port.\n");
312 irq_install_handler ( VECNUM_U0 /*UART0 *//*int vec */ ,
313 serial_isr /*interrupt_handler_t *handler */ ,
314 (void *) &buf_info /*void *arg */ );
316 /* Enable "RX Data Available" Interrupt on UART */
317 /* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */
318 outb(0x01, UART0_BASE + UART_IER);
320 /* Set DTR and RTS active, enable interrupts */
321 outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
323 /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
324 outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR);
326 serial_buffer_active = 1;
329 void serial_buffered_putc (const char c)
333 #if defined(CONFIG_HW_WATCHDOG)
334 while (!(inb (UART0_BASE + UART_MSR) & 0x10))
338 for (i=0;i<1000;i++) {
339 if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
347 if ((inb (UART0_BASE + UART_MSR) & 0x10)) {
356 void serial_buffered_puts(const char *s)
361 int serial_buffered_getc(void)
365 int rx_get = buf_info.rx_get;
368 #if defined(CONFIG_HW_WATCHDOG)
369 while (rx_get == buf_info.rx_put)
372 while (rx_get == buf_info.rx_put);
374 c = buf_info.rx_buffer[rx_get++];
375 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) {
378 buf_info.rx_get = rx_get;
380 rx_put = buf_info.rx_put;
381 if (rx_get <= rx_put) {
382 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
384 space = rx_get - rx_put;
386 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
387 /* Start flow by setting RTS active */
388 outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR);
394 int serial_buffered_tstc(void)
396 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
399 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
402 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
404 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
406 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
407 configuration has been already done
408 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
409 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
411 #if (CONFIG_KGDB_SER_INDEX & 2)
412 void kgdb_serial_init(void)
414 DECLARE_GLOBAL_DATA_PTR;
417 bdiv = serial_div (CONFIG_KGDB_BAUDRATE);
420 * Init onboard 16550 UART
422 outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */
423 outb(bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */
424 outb(bdiv >> 8), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */
425 outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */
426 outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */
427 outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */
428 val = inb(UART1_BASE + UART_LSR); /* clear line status */
429 val = inb(UART1_BASE + UART_RBR); /* read receive buffer */
430 outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */
431 outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */
435 void putDebugChar(const char c)
440 outb(c, UART1_BASE + UART_THR); /* put character out */
442 /* check THRE bit, wait for transfer done */
443 while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20);
447 void putDebugStr(const char *s)
455 int getDebugChar(void)
457 unsigned char status = 0;
460 status = inb(UART1_BASE + UART_LSR);
461 if ((status & asyncLSRDataReady1) != 0x0) {
464 if ((status & ( asyncLSRFramingError1 |
465 asyncLSROverrunError1 |
466 asyncLSRParityError1 |
467 asyncLSRBreakInterrupt1 )) != 0) {
468 outb(asyncLSRFramingError1 |
469 asyncLSROverrunError1 |
470 asyncLSRParityError1 |
471 asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR);
474 return (0x000000ff & (int) inb(UART1_BASE));
478 void kgdb_interruptible(int yes)
483 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
485 void kgdb_serial_init(void)
487 serial_printf ("[on serial] ");
490 void putDebugChar(int c)
495 void putDebugStr(const char *str)
500 int getDebugChar(void)
502 return serial_getc ();
505 void kgdb_interruptible(int yes)
509 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
510 #endif /* CFG_CMD_KGDB */