3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* stuff specific for the sc520,
25 * but idependent of implementation */
37 #include <asm/ic/sc520.h>
40 * utility functions for boards based on the AMD sc520
42 * void write_mmcr_byte(u16 mmcr, u8 data)
43 * void write_mmcr_word(u16 mmcr, u16 data)
44 * void write_mmcr_long(u16 mmcr, u32 data)
46 * u8 read_mmcr_byte(u16 mmcr)
47 * u16 read_mmcr_word(u16 mmcr)
48 * u32 read_mmcr_long(u16 mmcr)
50 * void init_sc520(void)
51 * unsigned long init_sc520_dram(void)
52 * void pci_sc520_init(struct pci_controller *hose)
54 * void reset_timer(void)
55 * ulong get_timer(ulong base)
56 * void set_timer(ulong t)
57 * void udelay(unsigned long usec)
61 static u32 mmcr_base= 0xfffef000;
63 void write_mmcr_byte(u16 mmcr, u8 data)
65 writeb(data, mmcr+mmcr_base);
68 void write_mmcr_word(u16 mmcr, u16 data)
70 writew(data, mmcr+mmcr_base);
73 void write_mmcr_long(u16 mmcr, u32 data)
75 writel(data, mmcr+mmcr_base);
78 u8 read_mmcr_byte(u16 mmcr)
80 return readb(mmcr+mmcr_base);
83 u16 read_mmcr_word(u16 mmcr)
85 return readw(mmcr+mmcr_base);
88 u32 read_mmcr_long(u16 mmcr)
90 return readl(mmcr+mmcr_base);
96 DECLARE_GLOBAL_DATA_PTR;
98 /* Set the UARTxCTL register at it's slower,
99 * baud clock giving us a 1.8432 MHz reference
101 write_mmcr_byte(SC520_UART1CTL, 7);
102 write_mmcr_byte(SC520_UART2CTL, 7);
104 /* first set the timer pin mapping */
105 write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
107 /* enable PCI bus arbitrer */
108 write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
110 write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
111 write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
114 if (CFG_SC520_HIGH_SPEED) {
115 write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
116 gd->cpu_clk = 133000000;
117 printf("## CPU Speed set to 133MHz\n");
119 write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
120 printf("## CPU Speed set to 100MHz\n");
121 gd->cpu_clk = 100000000;
125 /* wait at least one millisecond */
126 asm("movl $0x2000,%%ecx\n"
127 "wait_loop: pushl %%ecx\n"
129 "loop wait_loop\n": : : "ecx");
131 /* turn on the SDRAM write buffer */
132 write_mmcr_byte(SC520_DBCTL, 0x11);
134 /* turn on the cache and disable write through */
135 asm("movl %%cr0, %%eax\n"
136 "andl $0x9fffffff, %%eax\n"
137 "movl %%eax, %%cr0\n" : : : "eax");
140 unsigned long init_sc520_dram(void)
142 DECLARE_GLOBAL_DATA_PTR;
150 int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
151 int refresh_rate = CFG_SDRAM_REFRESH_RATE;
152 int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
154 /* set SDRAM speed here */
157 if (refresh_rate<=1) {
159 } else if (refresh_rate==2) {
160 val = 1; /* 15.6us */
161 } else if (refresh_rate==3 || refresh_rate==4) {
162 val = 2; /* 31.2us */
164 val = 3; /* 62.4us */
166 write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
168 val = read_mmcr_byte(SC520_DRCTMCTL);
171 if (cas_precharge_delay==3) {
172 val |= 0x04; /* 3T */
173 } else if (cas_precharge_delay==4) {
174 val |= 0x08; /* 4T */
175 } else if (cas_precharge_delay>4) {
179 if (ras_cas_delay > 3) {
184 write_mmcr_byte(SC520_DRCTMCTL, val);
187 /* We read-back the configuration of the dram
188 * controller that the assembly code wrote */
189 dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
192 bd->bi_dram[0].start = 0;
193 if (dram_ctrl & 0x80) {
195 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
196 bd->bi_dram[0].size = bd->bi_dram[1].start;
199 bd->bi_dram[0].size = 0;
200 bd->bi_dram[1].start = bd->bi_dram[0].start;
203 if (dram_ctrl & 0x8000) {
205 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
206 bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
208 bd->bi_dram[1].size = 0;
209 bd->bi_dram[2].start = bd->bi_dram[1].start;
212 if (dram_ctrl & 0x800000) {
214 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
215 bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
217 bd->bi_dram[2].size = 0;
218 bd->bi_dram[3].start = bd->bi_dram[2].start;
221 if (dram_ctrl & 0x80000000) {
223 dram_present = (dram_ctrl & 0x7f000000) >> 2;
224 bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
226 bd->bi_dram[3].size = 0;
231 printf("Configured %d bytes of dram\n", dram_present);
233 gd->ram_size = dram_present;
247 { SC520_IRQ0, SC520_MPICMODE, 0x01 },
248 { SC520_IRQ1, SC520_MPICMODE, 0x02 },
249 { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
250 { SC520_IRQ3, SC520_MPICMODE, 0x08 },
251 { SC520_IRQ4, SC520_MPICMODE, 0x10 },
252 { SC520_IRQ5, SC520_MPICMODE, 0x20 },
253 { SC520_IRQ6, SC520_MPICMODE, 0x40 },
254 { SC520_IRQ7, SC520_MPICMODE, 0x80 },
256 { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
257 { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
258 { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
259 { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
260 { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
261 { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
262 { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
263 { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
267 /* The interrupt used for PCI INTA-INTD */
268 int sc520_pci_ints[15] = {
269 -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, -1, -1, -1, -1, -1, -1
273 /* utility function to configure a pci interrupt */
274 int pci_sc520_set_irq(int pci_pin, int irq)
279 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
281 if (irq < 0 || irq > 15) {
282 return -1; /* illegal irq */
285 if (pci_pin < 0 || pci_pin > 15) {
286 return -1; /* illegal pci int pin */
289 /* first disable any non-pci interrupt source that use
291 for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
292 if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
295 if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
296 write_mmcr_byte(i, SC520_IRQ_DISABLED);
300 /* Set the trigger to level */
301 write_mmcr_byte(sc520_irq[irq].level_reg,
302 read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
307 /* route the interrupt */
308 write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
312 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
313 write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
315 /* also set the polarity in this case */
316 write_mmcr_word(SC520_INTPINPOL,
317 read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
321 /* register the pin */
322 sc520_pci_ints[pci_pin] = irq;
328 void pci_sc520_init(struct pci_controller *hose)
330 hose->first_busno = 0;
331 hose->last_busno = 0xff;
333 /* System memory space */
334 pci_set_region(hose->regions + 0,
335 SC520_PCI_MEMORY_BUS,
336 SC520_PCI_MEMORY_PHYS,
337 SC520_PCI_MEMORY_SIZE,
338 PCI_REGION_MEM | PCI_REGION_MEMORY);
340 /* PCI memory space */
341 pci_set_region(hose->regions + 1,
347 /* ISA/PCI memory space */
348 pci_set_region(hose->regions + 2,
355 pci_set_region(hose->regions + 3,
361 /* ISA/PCI I/O space */
362 pci_set_region(hose->regions + 4,
368 hose->region_count = 5;
370 pci_setup_type1(hose,
374 pci_register_hose(hose);
376 hose->last_busno = pci_hose_scan(hose);
378 /* enable target memory acceses on host brige */
379 pci_write_config_word(0, PCI_COMMAND,
380 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
388 #ifdef CFG_TIMER_SC520
391 void reset_timer(void)
393 write_mmcr_word(SC520_GPTMR0CNT, 0);
394 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
398 ulong get_timer(ulong base)
400 /* fixme: 30 or 33 */
401 return read_mmcr_word(SC520_GPTMR0CNT) / 33;
404 void set_timer(ulong t)
406 /* FixMe: use two cascade coupled timers */
407 write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
408 write_mmcr_word(SC520_GPTMR0CNT, t*33);
409 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
413 void udelay(unsigned long usec)
418 read_mmcr_word(SC520_SWTMRMILLI);
419 read_mmcr_word(SC520_SWTMRMICRO);
422 /* do not enable this line, udelay is used in the serial driver -> recursion */
423 printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
427 m += read_mmcr_word(SC520_SWTMRMILLI);
428 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
438 int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
443 temp |= CTL_CLK_SEL_4;
444 } else if (freq >= 4096) {
445 temp |= CTL_CLK_SEL_8;
446 } else if (freq >= 2048) {
447 temp |= CTL_CLK_SEL_16;
448 } else if (freq >= 1024) {
449 temp |= CTL_CLK_SEL_32;
450 } else if (freq >= 512) {
451 temp |= CTL_CLK_SEL_64;
452 } else if (freq >= 256) {
453 temp |= CTL_CLK_SEL_128;
454 } else if (freq >= 128) {
455 temp |= CTL_CLK_SEL_256;
457 temp |= CTL_CLK_SEL_512;
472 write_mmcr_byte(SC520_SSICTL, temp);
477 u8 ssi_txrx_byte(u8 data)
479 write_mmcr_byte(SC520_SSIXMIT, data);
480 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
481 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
482 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
483 return read_mmcr_byte(SC520_SSIRCV);
487 void ssi_tx_byte(u8 data)
489 write_mmcr_byte(SC520_SSIXMIT, data);
490 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
491 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
496 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
497 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
498 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
499 return read_mmcr_byte(SC520_SSIRCV);
502 #endif /* CONFIG_SC520 */