3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* stuff specific for the sc520,
25 * but idependent of implementation */
31 #ifdef CONFIG_SC520_SSI
32 #include <asm/ic/ssi.h>
36 #include <asm/ic/sc520.h>
38 DECLARE_GLOBAL_DATA_PTR;
41 * utility functions for boards based on the AMD sc520
43 * void write_mmcr_byte(u16 mmcr, u8 data)
44 * void write_mmcr_word(u16 mmcr, u16 data)
45 * void write_mmcr_long(u16 mmcr, u32 data)
47 * u8 read_mmcr_byte(u16 mmcr)
48 * u16 read_mmcr_word(u16 mmcr)
49 * u32 read_mmcr_long(u16 mmcr)
51 * void init_sc520(void)
52 * unsigned long init_sc520_dram(void)
53 * void pci_sc520_init(struct pci_controller *hose)
55 * void reset_timer(void)
56 * ulong get_timer(ulong base)
57 * void set_timer(ulong t)
58 * void udelay(unsigned long usec)
62 static u32 mmcr_base= 0xfffef000;
64 void write_mmcr_byte(u16 mmcr, u8 data)
66 writeb(data, mmcr+mmcr_base);
69 void write_mmcr_word(u16 mmcr, u16 data)
71 writew(data, mmcr+mmcr_base);
74 void write_mmcr_long(u16 mmcr, u32 data)
76 writel(data, mmcr+mmcr_base);
79 u8 read_mmcr_byte(u16 mmcr)
81 return readb(mmcr+mmcr_base);
84 u16 read_mmcr_word(u16 mmcr)
86 return readw(mmcr+mmcr_base);
89 u32 read_mmcr_long(u16 mmcr)
91 return readl(mmcr+mmcr_base);
97 /* Set the UARTxCTL register at it's slower,
98 * baud clock giving us a 1.8432 MHz reference
100 write_mmcr_byte(SC520_UART1CTL, 7);
101 write_mmcr_byte(SC520_UART2CTL, 7);
103 /* first set the timer pin mapping */
104 write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
106 /* enable PCI bus arbitrer */
107 write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
109 write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
110 write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
113 if (CONFIG_SYS_SC520_HIGH_SPEED) {
114 write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
115 gd->cpu_clk = 133000000;
116 printf("## CPU Speed set to 133MHz\n");
118 write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
119 printf("## CPU Speed set to 100MHz\n");
120 gd->cpu_clk = 100000000;
124 /* wait at least one millisecond */
125 asm("movl $0x2000,%%ecx\n"
126 "wait_loop: pushl %%ecx\n"
128 "loop wait_loop\n": : : "ecx");
130 /* turn on the SDRAM write buffer */
131 write_mmcr_byte(SC520_DBCTL, 0x11);
133 /* turn on the cache and disable write through */
134 asm("movl %%cr0, %%eax\n"
135 "andl $0x9fffffff, %%eax\n"
136 "movl %%eax, %%cr0\n" : : : "eax");
139 unsigned long init_sc520_dram(void)
145 #ifdef CONFIG_SYS_SDRAM_DRCTMCTL
146 /* these memory control registers are set up in the assember part,
147 * in sc520_asm.S, during 'mem_init'. If we muck with them here,
148 * after we are running a stack in RAM, we have troubles. Besides,
149 * these refresh and delay values are better ? simply specified
150 * outright in the include/configs/{cfg} file since the HW designer
151 * simply dictates it.
156 int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
157 int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
158 int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
160 /* set SDRAM speed here */
163 if (refresh_rate<=1) {
165 } else if (refresh_rate==2) {
166 val = 1; /* 15.6us */
167 } else if (refresh_rate==3 || refresh_rate==4) {
168 val = 2; /* 31.2us */
170 val = 3; /* 62.4us */
173 write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
175 val = read_mmcr_byte(SC520_DRCTMCTL);
178 if (cas_precharge_delay==3) {
179 val |= 0x04; /* 3T */
180 } else if (cas_precharge_delay==4) {
181 val |= 0x08; /* 4T */
182 } else if (cas_precharge_delay>4) {
186 if (ras_cas_delay > 3) {
191 write_mmcr_byte(SC520_DRCTMCTL, val);
194 /* We read-back the configuration of the dram
195 * controller that the assembly code wrote */
196 dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
198 bd->bi_dram[0].start = 0;
199 if (dram_ctrl & 0x80) {
201 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
202 bd->bi_dram[0].size = bd->bi_dram[1].start;
205 bd->bi_dram[0].size = 0;
206 bd->bi_dram[1].start = bd->bi_dram[0].start;
209 if (dram_ctrl & 0x8000) {
211 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
212 bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
214 bd->bi_dram[1].size = 0;
215 bd->bi_dram[2].start = bd->bi_dram[1].start;
218 if (dram_ctrl & 0x800000) {
220 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
221 bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
223 bd->bi_dram[2].size = 0;
224 bd->bi_dram[3].start = bd->bi_dram[2].start;
227 if (dram_ctrl & 0x80000000) {
229 dram_present = (dram_ctrl & 0x7f000000) >> 2;
230 bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
232 bd->bi_dram[3].size = 0;
237 printf("Configured %d bytes of dram\n", dram_present);
239 gd->ram_size = dram_present;
253 { SC520_IRQ0, SC520_MPICMODE, 0x01 },
254 { SC520_IRQ1, SC520_MPICMODE, 0x02 },
255 { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
256 { SC520_IRQ3, SC520_MPICMODE, 0x08 },
257 { SC520_IRQ4, SC520_MPICMODE, 0x10 },
258 { SC520_IRQ5, SC520_MPICMODE, 0x20 },
259 { SC520_IRQ6, SC520_MPICMODE, 0x40 },
260 { SC520_IRQ7, SC520_MPICMODE, 0x80 },
262 { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
263 { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
264 { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
265 { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
266 { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
267 { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
268 { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
269 { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
273 /* The interrupt used for PCI INTA-INTD */
274 int sc520_pci_ints[15] = {
275 -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, -1, -1, -1, -1, -1, -1
279 /* utility function to configure a pci interrupt */
280 int pci_sc520_set_irq(int pci_pin, int irq)
285 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
287 if (irq < 0 || irq > 15) {
288 return -1; /* illegal irq */
291 if (pci_pin < 0 || pci_pin > 15) {
292 return -1; /* illegal pci int pin */
295 /* first disable any non-pci interrupt source that use
297 for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
298 if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
301 if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
302 write_mmcr_byte(i, SC520_IRQ_DISABLED);
306 /* Set the trigger to level */
307 write_mmcr_byte(sc520_irq[irq].level_reg,
308 read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
313 /* route the interrupt */
314 write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
318 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
319 write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
321 /* also set the polarity in this case */
322 write_mmcr_word(SC520_INTPINPOL,
323 read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
327 /* register the pin */
328 sc520_pci_ints[pci_pin] = irq;
334 void pci_sc520_init(struct pci_controller *hose)
336 hose->first_busno = 0;
337 hose->last_busno = 0xff;
339 /* System memory space */
340 pci_set_region(hose->regions + 0,
341 SC520_PCI_MEMORY_BUS,
342 SC520_PCI_MEMORY_PHYS,
343 SC520_PCI_MEMORY_SIZE,
344 PCI_REGION_MEM | PCI_REGION_MEMORY);
346 /* PCI memory space */
347 pci_set_region(hose->regions + 1,
353 /* ISA/PCI memory space */
354 pci_set_region(hose->regions + 2,
361 pci_set_region(hose->regions + 3,
367 /* ISA/PCI I/O space */
368 pci_set_region(hose->regions + 4,
374 hose->region_count = 5;
376 pci_setup_type1(hose,
380 pci_register_hose(hose);
382 hose->last_busno = pci_hose_scan(hose);
384 /* enable target memory acceses on host brige */
385 pci_write_config_word(0, PCI_COMMAND,
386 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
393 #ifdef CONFIG_SYS_TIMER_SC520
396 void reset_timer(void)
398 write_mmcr_word(SC520_GPTMR0CNT, 0);
399 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
403 ulong get_timer(ulong base)
405 /* fixme: 30 or 33 */
406 return read_mmcr_word(SC520_GPTMR0CNT) / 33;
409 void set_timer(ulong t)
411 /* FixMe: use two cascade coupled timers */
412 write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
413 write_mmcr_word(SC520_GPTMR0CNT, t*33);
414 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
418 void udelay(unsigned long usec)
423 read_mmcr_word(SC520_SWTMRMILLI);
424 read_mmcr_word(SC520_SWTMRMICRO);
427 /* do not enable this line, udelay is used in the serial driver -> recursion */
428 printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
432 m += read_mmcr_word(SC520_SWTMRMILLI);
433 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
443 int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
448 temp |= CTL_CLK_SEL_4;
449 } else if (freq >= 4096) {
450 temp |= CTL_CLK_SEL_8;
451 } else if (freq >= 2048) {
452 temp |= CTL_CLK_SEL_16;
453 } else if (freq >= 1024) {
454 temp |= CTL_CLK_SEL_32;
455 } else if (freq >= 512) {
456 temp |= CTL_CLK_SEL_64;
457 } else if (freq >= 256) {
458 temp |= CTL_CLK_SEL_128;
459 } else if (freq >= 128) {
460 temp |= CTL_CLK_SEL_256;
462 temp |= CTL_CLK_SEL_512;
477 write_mmcr_byte(SC520_SSICTL, temp);
482 u8 ssi_txrx_byte(u8 data)
484 write_mmcr_byte(SC520_SSIXMIT, data);
485 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
486 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
487 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
488 return read_mmcr_byte(SC520_SSIRCV);
492 void ssi_tx_byte(u8 data)
494 write_mmcr_byte(SC520_SSIXMIT, data);
495 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
496 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
501 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
502 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
503 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
504 return read_mmcr_byte(SC520_SSIRCV);
507 #ifdef CONFIG_SYS_RESET_SC520
508 void reset_cpu(ulong addr)
510 printf("Resetting using SC520 MMCR\n");
511 /* Write a '1' to the SYS_RST of the RESCFG MMCR */
512 write_mmcr_word(SC520_RESCFG, 0x0001);