3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/i8259.h>
28 #include <asm/ibmpc.h>
29 #include <asm/interrupt.h>
38 } __attribute__ ((packed));
41 struct idt_entry idt[256];
46 typedef struct irq_handler {
47 struct irq_handler *next;
48 interrupt_handler_t* isr_func;
52 #define IRQ_DISABLED 1
55 irq_handler_t *handler;
59 static irq_desc_t irq_table[MAX_IRQ];
72 char exception_stack[4096];
74 #define DECLARE_INTERRUPT(x) \
75 asm(".globl irq_"#x"\n" \
79 "pushl $irq_return\n" \
81 void __attribute__ ((regparm(0))) irq_##x(void)
83 #define DECLARE_EXCEPTION(x, f) \
84 asm(".globl exp_"#x"\n" \
88 "movl $exception_stack, %eax\n" \
89 "movl %eax, %esp \n" \
91 "movl 32(%esp), %ebx\n" \
93 "movw 36(%esp), %dx\n" \
97 "pushl $exp_return\n" \
99 void __attribute__ ((regparm(0))) exp_##x(void)
101 DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */
102 DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */
103 DECLARE_EXCEPTION(2, nmi_entry); /* NMI */
104 DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */
105 DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */
106 DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */
107 DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */
108 DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */
109 DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */
110 DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */
111 DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
112 DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */
113 DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */
114 DECLARE_EXCEPTION(13, gpf_entry); /* GPF */
115 DECLARE_EXCEPTION(14, page_fault_entry); /* PF */
116 DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */
117 DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */
118 DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */
119 DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */
120 DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */
121 DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */
122 DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */
123 DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */
124 DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */
125 DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */
126 DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */
127 DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */
128 DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */
129 DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */
130 DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */
131 DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */
132 DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */
134 DECLARE_INTERRUPT(0);
135 DECLARE_INTERRUPT(1);
136 DECLARE_INTERRUPT(3);
137 DECLARE_INTERRUPT(4);
138 DECLARE_INTERRUPT(5);
139 DECLARE_INTERRUPT(6);
140 DECLARE_INTERRUPT(7);
141 DECLARE_INTERRUPT(8);
142 DECLARE_INTERRUPT(9);
143 DECLARE_INTERRUPT(10);
144 DECLARE_INTERRUPT(11);
145 DECLARE_INTERRUPT(12);
146 DECLARE_INTERRUPT(13);
147 DECLARE_INTERRUPT(14);
148 DECLARE_INTERRUPT(15);
150 void __attribute__ ((regparm(0))) default_isr(void);
151 asm ("default_isr: iret\n");
153 void disable_irq(int irq)
155 if (irq >= MAX_IRQ) {
158 irq_table[irq].status |= IRQ_DISABLED;
162 void enable_irq(int irq)
164 if (irq >= MAX_IRQ) {
167 irq_table[irq].status &= ~IRQ_DISABLED;
170 /* masks one specific IRQ in the PIC */
171 static void unmask_irq(int irq)
175 if (irq >= MAX_IRQ) {
179 imr_port = SLAVE_PIC + IMR;
181 imr_port = MASTER_PIC + IMR;
184 outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
188 /* unmasks one specific IRQ in the PIC */
189 static void mask_irq(int irq)
193 if (irq >= MAX_IRQ) {
197 imr_port = SLAVE_PIC + IMR;
199 imr_port = MASTER_PIC + IMR;
202 outb(inb(imr_port)|(1<<(irq&7)), imr_port);
206 /* issue a Specific End Of Interrupt instruciton */
207 static void specific_eoi(int irq)
209 /* If it is on the slave PIC this have to be performed on
210 * both the master and the slave PICs */
212 outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
213 irq = SEOI_IR2; /* also do IR2 on master */
215 outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
218 void __attribute__ ((regparm(0))) do_irq(int irq)
223 if (irq_table[irq].status & IRQ_DISABLED) {
230 if (NULL != irq_table[irq].handler) {
231 irq_handler_t *handler;
232 for (handler = irq_table[irq].handler;
233 NULL!= handler; handler = handler->next) {
234 handler->isr_func(handler->isr_data);
237 if ((irq & 7) != 7) {
238 printf("Spurious irq %d\n", irq);
246 void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
248 printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
251 void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
253 printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
257 void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
259 printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
262 void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
264 printf("NMI Interrupt at %04x:%08x\n", seg, ip);
267 void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
269 printf("Invalid Instruction at %04x:%08x\n", seg, ip);
273 void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
275 printf("Double fault at %04x:%08x\n", seg, ip);
279 void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
281 printf("Invalid TSS at %04x:%08x\n", seg, ip);
284 void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
286 printf("Segmentation fault at %04x:%08x\n", seg, ip);
290 void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
292 printf("Stack fault at %04x:%08x\n", seg, ip);
296 void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
298 printf("General protection fault at %04x:%08x\n", seg, ip);
301 void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
303 printf("Page fault at %04x:%08x\n", seg, ip);
307 void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
309 printf("Floating point exception at %04x:%08x\n", seg, ip);
312 void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
314 printf("Alignment check at %04x:%08x\n", seg, ip);
317 void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
319 printf("Machine check exception at %04x:%08x\n", seg, ip);
323 void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
331 if (NULL != irq_table[ino].handler) {
335 status = disable_interrupts();
336 irq_table[ino].handler = malloc(sizeof(irq_handler_t));
337 if (NULL == irq_table[ino].handler) {
341 memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
343 irq_table[ino].handler->isr_func = func;
344 irq_table[ino].handler->isr_data = pdata;
354 void irq_free_handler(int ino)
361 status = disable_interrupts();
363 if (NULL == irq_table[ino].handler) {
366 free(irq_table[ino].handler);
367 irq_table[ino].handler=NULL;
376 ".word 0x800\n" /* size of the table 8*256 bytes */
377 ".long idt\n" /* offset */
378 ".word 0x18\n");/* data segment */
380 void set_vector(int intnum, void *routine)
382 idt[intnum].base_high = (u16)((u32)(routine)>>16);
383 idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
387 int interrupt_init(void)
391 /* Just in case... */
392 disable_interrupts();
394 /* Initialize the IDT and stuff */
397 memset(irq_table, 0, sizeof(irq_table));
400 for (i=0;i<256;i++) {
401 idt[i].access = 0x8e;
403 idt[i].selector = 0x10;
404 set_vector(i, default_isr);
407 asm ("cs lidt idt_ptr\n");
409 /* Setup exceptions */
410 set_vector(0x00, exp_0);
411 set_vector(0x01, exp_1);
412 set_vector(0x02, exp_2);
413 set_vector(0x03, exp_3);
414 set_vector(0x04, exp_4);
415 set_vector(0x05, exp_5);
416 set_vector(0x06, exp_6);
417 set_vector(0x07, exp_7);
418 set_vector(0x08, exp_8);
419 set_vector(0x09, exp_9);
420 set_vector(0x0a, exp_10);
421 set_vector(0x0b, exp_11);
422 set_vector(0x0c, exp_12);
423 set_vector(0x0d, exp_13);
424 set_vector(0x0e, exp_14);
425 set_vector(0x0f, exp_15);
426 set_vector(0x10, exp_16);
427 set_vector(0x11, exp_17);
428 set_vector(0x12, exp_18);
429 set_vector(0x13, exp_19);
430 set_vector(0x14, exp_20);
431 set_vector(0x15, exp_21);
432 set_vector(0x16, exp_22);
433 set_vector(0x17, exp_23);
434 set_vector(0x18, exp_24);
435 set_vector(0x19, exp_25);
436 set_vector(0x1a, exp_26);
437 set_vector(0x1b, exp_27);
438 set_vector(0x1c, exp_28);
439 set_vector(0x1d, exp_29);
440 set_vector(0x1e, exp_30);
441 set_vector(0x1f, exp_31);
444 /* Setup interrupts */
445 set_vector(0x20, irq_0);
446 set_vector(0x21, irq_1);
447 set_vector(0x23, irq_3);
448 set_vector(0x24, irq_4);
449 set_vector(0x25, irq_5);
450 set_vector(0x26, irq_6);
451 set_vector(0x27, irq_7);
452 set_vector(0x28, irq_8);
453 set_vector(0x29, irq_9);
454 set_vector(0x2a, irq_10);
455 set_vector(0x2b, irq_11);
456 set_vector(0x2c, irq_12);
457 set_vector(0x2d, irq_13);
458 set_vector(0x2e, irq_14);
459 set_vector(0x2f, irq_15);
460 /* vectors 0x30-0x3f are reserved for irq 16-31 */
463 /* Mask all interrupts */
464 outb(0xff, MASTER_PIC + IMR);
465 outb(0xff, SLAVE_PIC + IMR);
468 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
469 outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
470 outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
471 outb(ICW4_PM, MASTER_PIC + ICW4);
474 outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
478 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
479 outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
480 outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
481 outb(ICW4_PM, SLAVE_PIC + ICW4);
484 outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
488 /* enable cascade interrerupt */
489 outb(0xfb, MASTER_PIC + IMR);
490 outb(0xff, SLAVE_PIC + IMR);
492 /* It is now safe to enable interrupts */
498 void enable_interrupts(void)
503 int disable_interrupts(void)
507 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
509 return (flags&0x200); /* IE flags is bit 9 */