2 * U-boot - start.S Startup file of u-boot for BF537
4 * Copyright (c) 2005-2007 Analog Devices Inc.
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
40 #include <linux/config.h>
42 #include <asm/blackfin.h>
51 .global _bf533_data_dest;
52 .global _bf533_data_size;
58 .global _icache_enable;
59 .global _dcache_enable;
60 #if defined(CONFIG_BF537)&&defined(CONFIG_POST)
61 .global _memory_post_test;
65 #if (BFIN_BOOT_MODE == BF537_UART_BOOT)
66 #if (CONFIG_CCLK_DIV == 1)
67 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
69 #if (CONFIG_CCLK_DIV == 2)
70 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
72 #if (CONFIG_CCLK_DIV == 4)
73 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
75 #if (CONFIG_CCLK_DIV == 8)
76 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
78 #ifndef CONFIG_CCLK_ACT_DIV
79 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
92 /* As per HW reference manual DAG registers,
93 * DATA and Address resgister shall be zero'd
94 * in initialization, after a reset state
96 r1 = 0; /* Data registers zero'd */
104 p0 = 0; /* Address registers zero'd */
111 i0 = 0; /* DAG Registers zero'd */
128 /* Set loop counters to zero, to make sure that
129 * hw loops are disabled.
137 /* Check soft reset status */
139 p0.l = SWRST & 0xFFFF;
143 if !cc jump no_soft_reset;
145 /* Clear Soft reset */
153 /* Clear EVT registers */
154 p0.h = (EVT_EMULATION_ADDR >> 16);
155 p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
159 LSETUP(4,4) lc0 = p1;
162 #if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
170 #if (BFIN_BOOT_MODE == BF537_UART_BOOT)
179 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
181 p0.h = hi(PLL_LOCKCNT);
182 p0.l = lo(PLL_LOCKCNT);
188 * Put SDRAM in self-refresh, incase anything is running
190 P2.H = hi(EBIU_SDGCTL);
191 P2.L = lo(EBIU_SDGCTL);
198 * Set PLL_CTL with the value that we calculate in R0
199 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
200 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
201 * - [7] = output delay (add 200ps of delay to mem signals)
202 * - [6] = input delay (add 200ps of input delay to mem signals)
203 * - [5] = PDWN : 1=All Clocks off
204 * - [3] = STOPCK : 1=Core Clock off
205 * - [1] = PLL_OFF : 1=Disable Power to PLL
206 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
207 * all other bits set to zero
210 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
211 r0 = r0 << 9; /* Shift it over, */
212 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
214 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
215 r1 = r1 << 8; /* Shift it over */
216 r0 = r1 | r0; /* add them all together */
219 p0.l = lo(PLL_CTL); /* Load the address */
220 cli r2; /* Disable interrupts */
222 w[p0] = r0.l; /* Set the value */
223 idle; /* Wait for the PLL to stablize */
224 sti r2; /* Enable interrupts */
231 if ! CC jump check_again;
233 /* Configure SCLK & CCLK Dividers */
234 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
242 * We now are running at speed, time to set the Async mem bank wait states
243 * This will speed up execution, since we are normally running from FLASH.
244 * we need to read MAC address from FLASH
246 p2.h = (EBIU_AMBCTL1 >> 16);
247 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
248 r0.h = (AMBCTL1VAL >> 16);
249 r0.l = (AMBCTL1VAL & 0xFFFF);
253 p2.h = (EBIU_AMBCTL0 >> 16);
254 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
255 r0.h = (AMBCTL0VAL >> 16);
256 r0.l = (AMBCTL0VAL & 0xFFFF);
260 p2.h = (EBIU_AMGCTL >> 16);
261 p2.l = (EBIU_AMGCTL & 0xffff);
266 #if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
267 sp.l = (0xffb01000 & 0xFFFF);
268 sp.h = (0xffb01000 >> 16);
274 #if defined(CONFIG_BF537)&&defined(CONFIG_POST)
275 /* DMA POST code to Hi of L1 SRAM */
277 /* P1 Points to the beginning of SYSTEM MMR Space */
278 P1.H = hi(SYSMMR_BASE);
279 P1.L = lo(SYSMMR_BASE);
285 R2 = R1 - R0; /* Count */
288 R1.H = (CFG_MONITOR_BASE >> 16);
289 R1.L = (CFG_MONITOR_BASE & 0xFFFF);
291 R1.H = (CFG_FLASH_BASE >> 16);
292 R1.L = (CFG_FLASH_BASE & 0xFFFF);
293 R0 = R0 + R1; /* Source Address */
294 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
295 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
296 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
297 /* Destination DMAConfig Value (8-bit words) */
298 R4.L = (DI_EN | WNR | DMAEN);
301 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
302 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
304 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
305 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
306 /* Set Source DMAConfig = DMA Enable,
307 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
308 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
310 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
311 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
312 /* Set Destination DMAConfig = DMA Enable,
313 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
314 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
317 p0.h = hi(MDMA_D0_IRQ_STATUS);
318 p0.l = lo(MDMA_D0_IRQ_STATUS);
321 if ! CC jump POST_DMA_DONE
324 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
326 /* DMA POST data to Hi of L1 SRAM */
331 R2 = R1 - R0; /* Count */
334 R1.H = (CFG_MONITOR_BASE >> 16);
335 R1.L = (CFG_MONITOR_BASE & 0xFFFF);
337 R1.H = (CFG_FLASH_BASE >> 16);
338 R1.L = (CFG_FLASH_BASE & 0xFFFF);
339 R0 = R0 + R1; /* Source Address */
340 R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
341 R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
342 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
343 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
346 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
347 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
349 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
350 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
351 /* Set Source DMAConfig = DMA Enable,
352 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
353 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
355 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
356 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
357 /* Set Destination DMAConfig = DMA Enable,
358 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
359 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
362 p0.h = hi(MDMA_D0_IRQ_STATUS);
363 p0.l = lo(MDMA_D0_IRQ_STATUS);
366 if ! CC jump POST_DATA_DMA_DONE
369 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
371 p0.l = _memory_post_test;
372 p0.h = _memory_post_test;
375 r7 = r0; /* save return value */
380 /* relocate into to RAM */
392 p2.l = (CFG_MONITOR_BASE & 0xffff);
393 p2.h = (CFG_MONITOR_BASE >> 16);
396 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
397 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
406 r0.h = (CONFIG_STACKBASE >> 16);
407 r0.l = (CONFIG_STACKBASE & 0xFFFF);
412 * This next section keeps the processor in supervisor mode
413 * during kernel boot. Switches to user mode at end of boot.
414 * See page 3-9 of Hardware Reference manual for documentation.
417 /* To keep ourselves in the supervisor mode */
418 p0.l = (EVT_IVG15_ADDR & 0xFFFF);
419 p0.h = (EVT_IVG15_ADDR >> 16);
425 p0.l = (IMASK & 0xFFFF);
426 p0.h = (IMASK >> 16);
427 r0.l = LO(IVG15_POS);
428 r0.h = HI(IVG15_POS);
444 /* Initialise General-Purpose I/O Modules on BF537
445 * Rev 0.0 Anomaly 05000212 - PORTx_FER,
446 * PORT_MUX Registers Do Not accept "writes" correctly
448 p0.h = hi(PORTF_FER);
449 p0.l = lo(PORTF_FER);
450 R0.L = W[P0]; /* Read */
456 W[P0] = R0.L; /* Write */
461 W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
467 p0.h = hi(PORTH_FER);
468 p0.l = lo(PORTH_FER);
469 R0.L = W[P0]; /* Read */
475 W[P0] = R0.L; /* Write */
480 W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
488 /* DMA reset code to Hi of L1 SRAM */
490 P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
491 P1.L = lo(SYSMMR_BASE);
493 R0.H = reset_start; /* Source Address (high) */
494 R0.L = reset_start; /* Source Address (low) */
497 R2 = R1 - R0; /* Count */
498 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
499 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
500 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
501 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
505 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
506 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
508 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
509 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
510 /* Set Source DMAConfig = DMA Enable,
511 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
512 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
514 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
515 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
516 /* Set Destination DMAConfig = DMA Enable,
517 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
518 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
521 p0.h = hi(MDMA_D0_IRQ_STATUS);
522 p0.l = lo(MDMA_D0_IRQ_STATUS);
525 if ! CC jump WAIT_DMA_DONE
528 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
530 /* Initialize BSS Section with 0 s */
540 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
542 if CC jump _clear_bss_skip;
549 #if defined(CONFIG_BF537)&&defined(CONFIG_POST)
561 p0.h = WDOG_CNT >> 16;
562 p0.l = WDOG_CNT & 0xffff;
565 p0.h = WDOG_CTL >> 16;
566 p0.l = WDOG_CTL & 0xffff;