3 #include <linux/config.h>
5 #include <asm/blackfin.h>
6 #include <asm/mem_init.h>
7 #include <asm/mach-common/bits/bootrom.h>
8 #include <asm/mach-common/bits/ebiu.h>
9 #include <asm/mach-common/bits/pll.h>
10 #include <asm/mach-common/bits/uart.h>
13 #if (BFIN_BOOT_MODE != BF537_UART_BOOT)
14 #if (CONFIG_CCLK_DIV == 1)
15 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
17 #if (CONFIG_CCLK_DIV == 2)
18 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
20 #if (CONFIG_CCLK_DIV == 4)
21 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
23 #if (CONFIG_CCLK_DIV == 8)
24 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
26 #ifndef CONFIG_CCLK_ACT_DIV
27 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
37 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
46 r0.l = CONFIG_SPI_BAUD_INITBLOCK;
51 #if (BFIN_BOOT_MODE != BF537_UART_BOOT)
54 /* Enable PHY CLK buffer output */
63 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
65 p0.h = hi(PLL_LOCKCNT);
66 p0.l = lo(PLL_LOCKCNT);
72 * Put SDRAM in self-refresh, incase anything is running
74 P2.H = hi(EBIU_SDGCTL);
75 P2.L = lo(EBIU_SDGCTL);
82 * Set PLL_CTL with the value that we calculate in R0
83 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
84 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
85 * - [7] = output delay (add 200ps of delay to mem signals)
86 * - [6] = input delay (add 200ps of input delay to mem signals)
87 * - [5] = PDWN : 1=All Clocks off
88 * - [3] = STOPCK : 1=Core Clock off
89 * - [1] = PLL_OFF : 1=Disable Power to PLL
90 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
91 * all other bits set to zero
94 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
95 r0 = r0 << 9; /* Shift it over */
96 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
98 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
99 r1 = r1 << 8; /* Shift it over */
100 r0 = r1 | r0; /* add them all together */
103 p0.l = lo(PLL_CTL); /* Load the address */
104 cli r2; /* Disable interrupts */
106 w[p0] = r0.l; /* Set the value */
107 idle; /* Wait for the PLL to stablize */
108 sti r2; /* Enable interrupts */
115 if ! CC jump check_again;
117 /* Configure SCLK & CCLK Dividers */
118 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
126 * We now are running at speed, time to set the Async mem bank wait states
127 * This will speed up execution, since we are normally running from FLASH.
130 p2.h = (EBIU_AMBCTL1 >> 16);
131 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
132 r0.h = (AMBCTL1VAL >> 16);
133 r0.l = (AMBCTL1VAL & 0xFFFF);
137 p2.h = (EBIU_AMBCTL0 >> 16);
138 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
139 r0.h = (AMBCTL0VAL >> 16);
140 r0.l = (AMBCTL0VAL & 0xFFFF);
144 p2.h = (EBIU_AMGCTL >> 16);
145 p2.l = (EBIU_AMGCTL & 0xffff);
151 * Now, Initialize the SDRAM,
152 * start with the SDRAM Refresh Rate Control Register
154 p0.l = lo(EBIU_SDRRC);
155 p0.h = hi(EBIU_SDRRC);
161 * SDRAM Memory Bank Control Register - bank specific parameters
163 p0.l = (EBIU_SDBCTL & 0xFFFF);
164 p0.h = (EBIU_SDBCTL >> 16);
170 * SDRAM Global Control Register - global programmable parameters
171 * Disable self-refresh
173 P2.H = hi(EBIU_SDGCTL);
174 P2.L = lo(EBIU_SDGCTL);
179 * Check if SDRAM is already powered up, if it is, enable self-refresh
181 p0.h = hi(EBIU_SDSTAT);
182 p0.l = lo(EBIU_SDSTAT);
192 /* Write in the new value in the register */
193 R0.L = lo(mem_SDGCTL);
194 R0.H = hi(mem_SDGCTL);