1 /****************************************************************
2 * $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ *
6 * Maintainer: sonicz <sonic.zhang@analog.com> *
8 * CopyRight (c) 2006 Analog Device *
9 * All rights reserved. *
11 * This file is free software; *
12 * you are free to modify and/or redistribute it *
13 * under the terms of the GNU General Public Licence (GPL).*
15 ****************************************************************/
19 #ifdef CONFIG_HARD_I2C
21 #include <asm/blackfin.h>
25 #define bfin_read16(addr) ({ unsigned __v; \
26 __asm__ __volatile__ (\
27 "%0 = w[%1] (z);\n\t"\
28 : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
30 #define bfin_write16(addr,val) ({\
31 __asm__ __volatile__ (\
33 : : "a"(addr) , "d"(val) : "memory");})
35 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
36 #define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
37 #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
38 #define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
39 #define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
40 #define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
41 #define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
42 #define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
43 #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
44 #define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
45 #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
46 #define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
47 #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
48 #define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
49 #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
50 #define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
51 #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
52 #define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
53 #define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
54 #define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
55 #define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
56 #define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
57 #define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
58 #define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
59 #define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
60 #define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
61 #define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
62 #define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
63 #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
64 #define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
65 #define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
66 #define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
67 #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
70 #define PRINTD(fmt,args...) do { \
71 DECLARE_GLOBAL_DATA_PTR; \
72 if (gd->have_console) \
73 printf(fmt ,##args); \
76 #define PRINTD(fmt,args...)
79 #ifndef CONFIG_TWICLK_KHZ
80 #define CONFIG_TWICLK_KHZ 50
83 /* All transfers are described by this data structure */
85 u16 addr; /* slave address */
87 #define I2C_M_STOP 0x2
89 u16 len; /* msg length */
90 u8 *buf; /* pointer to msg data */
94 * i2c_reset: - reset the host controller
98 static void i2c_reset(void)
101 bfin_write_TWI_CONTROL(0);
104 /* Set TWI internal clock as 10MHz */
105 bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
107 /* Set Twi interface clock as specified */
108 if (CONFIG_TWICLK_KHZ > 400)
109 bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
112 bfin_write_TWI_CLKDIV(((5 * 1024 /
113 CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 /
118 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
122 int wait_for_completion(struct i2c_msg *msg, int timeout_count)
124 unsigned short twi_int_stat;
125 unsigned short mast_stat;
128 for (i = 0; i < timeout_count; i++) {
129 twi_int_stat = bfin_read_TWI_INT_STAT();
130 mast_stat = bfin_read_TWI_MASTER_STAT();
132 if (XMTSERV & twi_int_stat) {
133 /* Transmit next data */
135 bfin_write_TWI_XMT_DATA8(*(msg->buf++));
137 } else if (msg->flags & I2C_M_STOP)
138 bfin_write_TWI_MASTER_CTL
139 (bfin_read_TWI_MASTER_CTL() | STOP);
142 bfin_write_TWI_INT_STAT(XMTSERV);
146 if (RCVSERV & twi_int_stat) {
148 /* Receive next data */
149 *(msg->buf++) = bfin_read_TWI_RCV_DATA8();
151 } else if (msg->flags & I2C_M_STOP) {
152 bfin_write_TWI_MASTER_CTL
153 (bfin_read_TWI_MASTER_CTL() | STOP);
156 /* Clear interrupt source */
157 bfin_write_TWI_INT_STAT(RCVSERV);
161 if (MERR & twi_int_stat) {
162 bfin_write_TWI_INT_STAT(MERR);
163 bfin_write_TWI_INT_MASK(0);
164 bfin_write_TWI_MASTER_STAT(0x3e);
165 bfin_write_TWI_MASTER_CTL(0);
168 * if both err and complete int stats are set,
169 * return proper results.
171 if (MCOMP & twi_int_stat) {
172 bfin_write_TWI_INT_STAT(MCOMP);
173 bfin_write_TWI_INT_MASK(0);
174 bfin_write_TWI_MASTER_CTL(0);
177 * If it is a quick transfer,
178 * only address bug no data, not an err.
180 if (msg->len == 0 && mast_stat & BUFRDERR)
183 * If address not acknowledged return -3,
186 else if (!(mast_stat & ANAK))
193 if (MCOMP & twi_int_stat) {
194 bfin_write_TWI_INT_STAT(MCOMP);
196 bfin_write_TWI_INT_MASK(0);
197 bfin_write_TWI_MASTER_CTL(0);
202 if (msg->flags & I2C_M_RD)
209 * i2c_transfer: - Transfer one byte over the i2c bus
211 * This function can tranfer a byte over the i2c bus in both directions.
212 * It is used by the public API functions.
214 * @return: 0: transfer successful
216 * -2: transmit timeout
218 * -4: receive timeout
219 * -5: controller not ready
221 int i2c_transfer(struct i2c_msg *msg)
224 int timeout_count = 10000;
227 if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
232 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
234 /* Set Transmit device address */
235 bfin_write_TWI_MASTER_ADDR(msg->addr);
239 * Data in FIFO should be discarded before start a new operation.
241 bfin_write_TWI_FIFO_CTL(0x3);
243 bfin_write_TWI_FIFO_CTL(0);
246 if (!(msg->flags & I2C_M_RD)) {
247 /* Transmit first data */
249 PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
251 bfin_write_TWI_XMT_DATA8(*(msg->buf++));
258 bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
260 /* Interrupt mask . Enable XMT, RCV interrupt */
261 bfin_write_TWI_INT_MASK(MCOMP | MERR |
262 ((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
265 if (len > 0 && len <= 255)
266 bfin_write_TWI_MASTER_CTL((len << 6));
267 else if (msg->len > 255) {
268 bfin_write_TWI_MASTER_CTL((0xff << 6));
269 msg->flags &= I2C_M_STOP;
271 bfin_write_TWI_MASTER_CTL(0);
274 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
275 ((msg->flags & I2C_M_RD)
276 ? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
280 ret = wait_for_completion(msg, timeout_count);
281 PRINTD("3 in i2c_transfer: ret=%d\n", ret);
286 PRINTD(("i2c_transfer: error: transfer fail\n"));
289 PRINTD(("i2c_transfer: error: transmit timeout\n"));
292 PRINTD(("i2c_transfer: error: ACK missing\n"));
295 PRINTD(("i2c_transfer: error: receive timeout\n"));
298 PRINTD(("i2c_transfer: error: controller not ready\n"));
308 /* ---------------------------------------------------------------------*/
310 /* ---------------------------------------------------------------------*/
312 void i2c_init(int speed, int slaveaddr)
318 * i2c_probe: - Test if a chip answers for a given i2c address
320 * @chip: address of the chip which is searched for
321 * @return: 0 if a chip was found, -1 otherwhise
324 int i2c_probe(uchar chip)
336 if (i2c_transfer(&msg))
340 msg.flags = I2C_M_RD;
343 if (i2c_transfer(&msg))
350 * i2c_read: - Read multiple bytes from an i2c device
352 * chip: I2C chip address, range 0..127
353 * addr: Memory (register) address within the chip
354 * alen: Number of bytes to use for addr (typically 1, 2 for larger
355 * memories, 0 for register type devices with only one
357 * buffer: Where to read/write the data
358 * len: How many bytes to read/write
360 * Returns: 0 on success, not 0 on failure
363 int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
366 u8 addr_bytes[3]; /* lowest...highest byte of data address */
368 PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
372 addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
373 addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
374 addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
378 msg.buf = addr_bytes;
379 if (i2c_transfer(&msg))
383 /* start read sequence */
384 PRINTD(("i2c_read: start read sequence\n"));
386 msg.flags = I2C_M_RD;
389 if (i2c_transfer(&msg))
396 * i2c_write: - Write multiple bytes to an i2c device
398 * chip: I2C chip address, range 0..127
399 * addr: Memory (register) address within the chip
400 * alen: Number of bytes to use for addr (typically 1, 2 for larger
401 * memories, 0 for register type devices with only one
403 * buffer: Where to read/write the data
404 * len: How many bytes to read/write
406 * Returns: 0 on success, not 0 on failure
409 int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
412 u8 addr_bytes[3]; /* lowest...highest byte of data address */
415 ("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
416 chip, addr, alen, len, buffer[0]);
418 /* chip address write */
420 addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
421 addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
422 addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
426 msg.buf = addr_bytes;
427 if (i2c_transfer(&msg))
431 /* start read sequence */
432 PRINTD(("i2c_write: start write sequence\n"));
437 if (i2c_transfer(&msg))
444 uchar i2c_reg_read(uchar chip, uchar reg)
448 PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg);
449 i2c_read(chip, reg, 0, &buf, 1);
453 void i2c_reg_write(uchar chip, uchar reg, uchar val)
455 PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
457 i2c_write(chip, reg, 0, &val, 1);
460 #endif /* CONFIG_HARD_I2C */