2 * U-boot - start.S Startup file of u-boot for BF533/BF561
4 * Copyright (c) 2005-2007 Analog Devices Inc.
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
40 #include <linux/config.h>
42 #include <asm/blackfin.h>
44 #include <asm/mach-common/bits/core.h>
45 #include <asm/mach-common/bits/dma.h>
46 #include <asm/mach-common/bits/pll.h>
56 #if (CONFIG_CCLK_DIV == 1)
57 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
59 #if (CONFIG_CCLK_DIV == 2)
60 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
62 #if (CONFIG_CCLK_DIV == 4)
63 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
65 #if (CONFIG_CCLK_DIV == 8)
66 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
68 #ifndef CONFIG_CCLK_ACT_DIV
69 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
81 /* As per HW reference manual DAG registers,
82 * DATA and Address resgister shall be zero'd
83 * in initialization, after a reset state
85 r1 = 0; /* Data registers zero'd */
93 p0 = 0; /* Address registers zero'd */
100 i0 = 0; /* DAG Registers zero'd */
117 /* Set loop counters to zero, to make sure that
118 * hw loops are disabled.
126 /* Check soft reset status */
128 p0.l = SWRST & 0xFFFF;
132 if !cc jump no_soft_reset;
134 /* Clear Soft reset */
142 /* Clear EVT registers */
144 p0.l = (EVT0 & 0xFFFF);
148 LSETUP(4,4) lc0 = p1;
157 sp.l = (0xffb01000 & 0xFFFF);
158 sp.h = (0xffb01000 >> 16);
162 /* relocate into to RAM */
174 p2.l = (CFG_MONITOR_BASE & 0xffff);
175 p2.h = (CFG_MONITOR_BASE >> 16);
178 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
179 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
188 r0.h = (CONFIG_STACKBASE >> 16);
189 r0.l = (CONFIG_STACKBASE & 0xFFFF);
194 * This next section keeps the processor in supervisor mode
195 * during kernel boot. Switches to user mode at end of boot.
196 * See page 3-9 of Hardware Reference manual for documentation.
199 /* To keep ourselves in the supervisor mode */
200 p0.l = (EVT15 & 0xFFFF);
201 p0.h = (EVT15 >> 16);
207 p0.l = (IMASK & 0xFFFF);
208 p0.h = (IMASK >> 16);
209 r0.l = LO(EVT_IVG15);
210 r0.h = HI(EVT_IVG15);
225 /* DMA reset code to Hi of L1 SRAM */
227 /* P1 Points to the beginning of SYSTEM MMR Space */
228 P1.H = hi(SYSMMR_BASE);
229 P1.L = lo(SYSMMR_BASE);
231 R0.H = reset_start; /* Source Address (high) */
232 R0.L = reset_start; /* Source Address (low) */
235 R2 = R1 - R0; /* Count */
236 R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
237 R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
238 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
239 /* Destination DMAConfig Value (8-bit words) */
240 R4.L = (DI_EN | WNR | DMAEN);
244 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
245 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
247 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
248 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
249 /* Set Source DMAConfig = DMA Enable,
250 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
251 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
253 /* Set Destination Base Address */
254 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
255 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
256 /* Set Destination DMAConfig = DMA Enable,
257 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
258 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
261 p0.h = hi(MDMA_D0_IRQ_STATUS);
262 p0.l = lo(MDMA_D0_IRQ_STATUS);
265 if ! CC jump WAIT_DMA_DONE
269 /* Write 1 to clear DMA interrupt */
270 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
272 /* Initialize BSS Section with 0 s */
282 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
284 if CC jump _clear_bss_skip;
296 p0.h = WDOG_CNT >> 16;
297 p0.l = WDOG_CNT & 0xffff;
300 p0.h = WDOG_CTL >> 16;
301 p0.l = WDOG_CTL & 0xffff;