2 * U-boot - start.S Startup file of u-boot for BF533/BF561
4 * Copyright (c) 2005 blackfin.uclinux.org
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
40 #include <linux/config.h>
42 #include <asm/blackfin.h>
51 .global _bf533_data_dest;
52 .global _bf533_data_size;
59 #if (CONFIG_CCLK_DIV == 1)
60 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
62 #if (CONFIG_CCLK_DIV == 2)
63 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
65 #if (CONFIG_CCLK_DIV == 4)
66 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
68 #if (CONFIG_CCLK_DIV == 8)
69 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
71 #ifndef CONFIG_CCLK_ACT_DIV
72 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
84 /* As per HW reference manual DAG registers,
85 * DATA and Address resgister shall be zero'd
86 * in initialization, after a reset state
88 r1 = 0; /* Data registers zero'd */
96 p0 = 0; /* Address registers zero'd */
103 i0 = 0; /* DAG Registers zero'd */
120 /* Set loop counters to zero, to make sure that
121 * hw loops are disabled.
129 /* Check soft reset status */
131 p0.l = SWRST & 0xFFFF;
135 if !cc jump no_soft_reset;
137 /* Clear Soft reset */
145 /* Clear EVT registers */
146 p0.h = (EVT_EMULATION_ADDR >> 16);
147 p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
151 LSETUP(4,4) lc0 = p1;
160 sp.l = (0xffb01000 & 0xFFFF);
161 sp.h = (0xffb01000 >> 16);
165 /* relocate into to RAM */
177 p2.l = (CFG_MONITOR_BASE & 0xffff);
178 p2.h = (CFG_MONITOR_BASE >> 16);
181 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
182 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
191 r0.h = (CONFIG_STACKBASE >> 16);
192 r0.l = (CONFIG_STACKBASE & 0xFFFF);
197 * This next section keeps the processor in supervisor mode
198 * during kernel boot. Switches to user mode at end of boot.
199 * See page 3-9 of Hardware Reference manual for documentation.
202 /* To keep ourselves in the supervisor mode */
203 p0.l = (EVT_IVG15_ADDR & 0xFFFF);
204 p0.h = (EVT_IVG15_ADDR >> 16);
210 p0.l = (IMASK & 0xFFFF);
211 p0.h = (IMASK >> 16);
212 r0.l = LO(IVG15_POS);
213 r0.h = HI(IVG15_POS);
228 /* DMA reset code to Hi of L1 SRAM */
230 /* P1 Points to the beginning of SYSTEM MMR Space */
231 P1.H = hi(SYSMMR_BASE);
232 P1.L = lo(SYSMMR_BASE);
234 R0.H = reset_start; /* Source Address (high) */
235 R0.L = reset_start; /* Source Address (low) */
238 R2 = R1 - R0; /* Count */
239 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
240 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
241 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
242 /* Destination DMAConfig Value (8-bit words) */
243 R4.L = (DI_EN | WNR | DMAEN);
247 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
248 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
250 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
251 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
252 /* Set Source DMAConfig = DMA Enable,
253 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
254 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
256 /* Set Destination Base Address */
257 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
258 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
259 /* Set Destination DMAConfig = DMA Enable,
260 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
261 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
264 p0.h = hi(MDMA_D0_IRQ_STATUS);
265 p0.l = lo(MDMA_D0_IRQ_STATUS);
268 if ! CC jump WAIT_DMA_DONE
272 /* Write 1 to clear DMA interrupt */
273 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
275 /* Initialize BSS Section with 0 s */
285 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
287 if CC jump _clear_bss_skip;
299 p0.h = WDOG_CNT >> 16;
300 p0.l = WDOG_CNT & 0xffff;
303 p0.h = WDOG_CTL >> 16;
304 p0.l = WDOG_CTL & 0xffff;