2 * U-boot - start.S Startup file of u-boot for BF533/BF561
4 * Copyright (c) 2005-2007 Analog Devices Inc.
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
40 #include <linux/config.h>
42 #include <asm/blackfin.h>
44 #include <asm/mach-common/bits/core.h>
45 #include <asm/mach-common/bits/dma.h>
46 #include <asm/mach-common/bits/pll.h>
55 .global _bf533_data_dest;
56 .global _bf533_data_size;
63 #if (CONFIG_CCLK_DIV == 1)
64 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
66 #if (CONFIG_CCLK_DIV == 2)
67 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
69 #if (CONFIG_CCLK_DIV == 4)
70 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
72 #if (CONFIG_CCLK_DIV == 8)
73 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
75 #ifndef CONFIG_CCLK_ACT_DIV
76 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
88 /* As per HW reference manual DAG registers,
89 * DATA and Address resgister shall be zero'd
90 * in initialization, after a reset state
92 r1 = 0; /* Data registers zero'd */
100 p0 = 0; /* Address registers zero'd */
107 i0 = 0; /* DAG Registers zero'd */
124 /* Set loop counters to zero, to make sure that
125 * hw loops are disabled.
133 /* Check soft reset status */
135 p0.l = SWRST & 0xFFFF;
139 if !cc jump no_soft_reset;
141 /* Clear Soft reset */
149 /* Clear EVT registers */
151 p0.l = (EVT0 & 0xFFFF);
155 LSETUP(4,4) lc0 = p1;
164 sp.l = (0xffb01000 & 0xFFFF);
165 sp.h = (0xffb01000 >> 16);
169 /* relocate into to RAM */
181 p2.l = (CFG_MONITOR_BASE & 0xffff);
182 p2.h = (CFG_MONITOR_BASE >> 16);
185 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
186 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
195 r0.h = (CONFIG_STACKBASE >> 16);
196 r0.l = (CONFIG_STACKBASE & 0xFFFF);
201 * This next section keeps the processor in supervisor mode
202 * during kernel boot. Switches to user mode at end of boot.
203 * See page 3-9 of Hardware Reference manual for documentation.
206 /* To keep ourselves in the supervisor mode */
207 p0.l = (EVT15 & 0xFFFF);
208 p0.h = (EVT15 >> 16);
214 p0.l = (IMASK & 0xFFFF);
215 p0.h = (IMASK >> 16);
216 r0.l = LO(EVT_IVG15);
217 r0.h = HI(EVT_IVG15);
232 /* DMA reset code to Hi of L1 SRAM */
234 /* P1 Points to the beginning of SYSTEM MMR Space */
235 P1.H = hi(SYSMMR_BASE);
236 P1.L = lo(SYSMMR_BASE);
238 R0.H = reset_start; /* Source Address (high) */
239 R0.L = reset_start; /* Source Address (low) */
242 R2 = R1 - R0; /* Count */
243 R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
244 R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
245 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
246 /* Destination DMAConfig Value (8-bit words) */
247 R4.L = (DI_EN | WNR | DMAEN);
251 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
252 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
254 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
255 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
256 /* Set Source DMAConfig = DMA Enable,
257 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
258 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
260 /* Set Destination Base Address */
261 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
262 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
263 /* Set Destination DMAConfig = DMA Enable,
264 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
265 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
268 p0.h = hi(MDMA_D0_IRQ_STATUS);
269 p0.l = lo(MDMA_D0_IRQ_STATUS);
272 if ! CC jump WAIT_DMA_DONE
276 /* Write 1 to clear DMA interrupt */
277 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
279 /* Initialize BSS Section with 0 s */
289 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
291 if CC jump _clear_bss_skip;
303 p0.h = WDOG_CNT >> 16;
304 p0.l = WDOG_CNT & 0xffff;
307 p0.h = WDOG_CTL >> 16;
308 p0.l = WDOG_CTL & 0xffff;