3 #include <linux/config.h>
5 #include <asm/blackfin.h>
6 #include <asm/mem_init.h>
7 #include <asm/mach-common/bits/bootrom.h>
8 #include <asm/mach-common/bits/ebiu.h>
9 #include <asm/mach-common/bits/pll.h>
10 #include <asm/mach-common/bits/uart.h>
13 #if (CONFIG_CCLK_DIV == 1)
14 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
16 #if (CONFIG_CCLK_DIV == 2)
17 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
19 #if (CONFIG_CCLK_DIV == 4)
20 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
22 #if (CONFIG_CCLK_DIV == 8)
23 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
25 #ifndef CONFIG_CCLK_ACT_DIV
26 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
35 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
38 r0.l = CONFIG_SPI_BAUD_INITBLOCK;
44 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
46 p0.h = hi(PLL_LOCKCNT);
47 p0.l = lo(PLL_LOCKCNT);
53 * Put SDRAM in self-refresh, incase anything is running
55 P2.H = hi(EBIU_SDGCTL);
56 P2.L = lo(EBIU_SDGCTL);
63 * Set PLL_CTL with the value that we calculate in R0
64 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
65 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
66 * - [7] = output delay (add 200ps of delay to mem signals)
67 * - [6] = input delay (add 200ps of input delay to mem signals)
68 * - [5] = PDWN : 1=All Clocks off
69 * - [3] = STOPCK : 1=Core Clock off
70 * - [1] = PLL_OFF : 1=Disable Power to PLL
71 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
72 * all other bits set to zero
75 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
76 r0 = r0 << 9; /* Shift it over, */
77 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
79 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
80 r1 = r1 << 8; /* Shift it over */
81 r0 = r1 | r0; /* add them all together */
84 p0.l = lo(PLL_CTL); /* Load the address */
85 cli r2; /* Disable interrupts */
87 w[p0] = r0.l; /* Set the value */
88 idle; /* Wait for the PLL to stablize */
89 sti r2; /* Enable interrupts */
96 if ! CC jump check_again;
98 /* Configure SCLK & CCLK Dividers */
99 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
106 * We now are running at speed, time to set the Async mem bank wait states
107 * This will speed up execution, since we are normally running from FLASH.
110 p2.h = (EBIU_AMBCTL1 >> 16);
111 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
112 r0.h = (AMBCTL1VAL >> 16);
113 r0.l = (AMBCTL1VAL & 0xFFFF);
117 p2.h = (EBIU_AMBCTL0 >> 16);
118 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
119 r0.h = (AMBCTL0VAL >> 16);
120 r0.l = (AMBCTL0VAL & 0xFFFF);
124 p2.h = (EBIU_AMGCTL >> 16);
125 p2.l = (EBIU_AMGCTL & 0xffff);
131 * Now, Initialize the SDRAM,
132 * start with the SDRAM Refresh Rate Control Register
134 p0.l = lo(EBIU_SDRRC);
135 p0.h = hi(EBIU_SDRRC);
141 * SDRAM Memory Bank Control Register - bank specific parameters
143 p0.l = (EBIU_SDBCTL & 0xFFFF);
144 p0.h = (EBIU_SDBCTL >> 16);
150 * SDRAM Global Control Register - global programmable parameters
151 * Disable self-refresh
153 P2.H = hi(EBIU_SDGCTL);
154 P2.L = lo(EBIU_SDGCTL);
159 * Check if SDRAM is already powered up, if it is, enable self-refresh
161 p0.h = hi(EBIU_SDSTAT);
162 p0.l = lo(EBIU_SDSTAT);
172 /* Write in the new value in the register */
173 R0.L = lo(mem_SDGCTL);
174 R0.H = hi(mem_SDGCTL);