cpu/bf533/cpu.c

   1 /*
   2  * U-boot - cpu.c CPU specific functions
   3  *
   4  * Copyright (c) 2005 blackfin.uclinux.org
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/blackfin.h>
  30 #include <command.h>
  31 #include <asm/entry.h>
  32
  33 #define SSYNC() asm("ssync;")
  34 #define CACHE_ON 1
  35 #define CACHE_OFF 0
  36
  37 /* Data Attibutes*/
  38
  39 #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
  40 #define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  41 #define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  42 #define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
  43
  44 #define ANOMALY_05000158                0x200
  45 #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
  46 #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
  47 #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
  48 #define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
  49 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
  50
  51 static unsigned int icplb_table[16][2]={
  52                         {0xFFA00000, L1_IMEMORY},
  53                         {0x00000000, SDRAM_IKERNEL},    /*SDRAM_Page1*/
  54                         {0x00400000, SDRAM_IKERNEL},    /*SDRAM_Page1*/
  55                         {0x07C00000, SDRAM_IKERNEL},    /*SDRAM_Page14*/
  56                         {0x00800000, SDRAM_IGENERIC},   /*SDRAM_Page2*/
  57                         {0x00C00000, SDRAM_IGENERIC},   /*SDRAM_Page2*/
  58                         {0x01000000, SDRAM_IGENERIC},   /*SDRAM_Page4*/
  59                         {0x01400000, SDRAM_IGENERIC},   /*SDRAM_Page5*/
  60                         {0x01800000, SDRAM_IGENERIC},   /*SDRAM_Page6*/
  61                         {0x01C00000, SDRAM_IGENERIC},   /*SDRAM_Page7*/
  62                         {0x02000000, SDRAM_IGENERIC},   /*SDRAM_Page8*/
  63                         {0x02400000, SDRAM_IGENERIC},   /*SDRAM_Page9*/
  64                         {0x02800000, SDRAM_IGENERIC},   /*SDRAM_Page10*/
  65                         {0x02C00000, SDRAM_IGENERIC},   /*SDRAM_Page11*/
  66                         {0x03000000, SDRAM_IGENERIC},   /*SDRAM_Page12*/
  67                         {0x03400000, SDRAM_IGENERIC},   /*SDRAM_Page13*/
  68 };
  69
  70 static unsigned int dcplb_table[16][2]={
  71                         {0xFFA00000,L1_DMEMORY},
  72                         {0x00000000,SDRAM_DKERNEL},     /*SDRAM_Page1*/
  73                         {0x00400000,SDRAM_DKERNEL},     /*SDRAM_Page1*/
  74                         {0x07C00000,SDRAM_DKERNEL},     /*SDRAM_Page15*/
  75                         {0x00800000,SDRAM_DGENERIC},    /*SDRAM_Page2*/
  76                         {0x00C00000,SDRAM_DGENERIC},    /*SDRAM_Page3*/
  77                         {0x01000000,SDRAM_DGENERIC},    /*SDRAM_Page4*/
  78                         {0x01400000,SDRAM_DGENERIC},    /*SDRAM_Page5*/
  79                         {0x01800000,SDRAM_DGENERIC},    /*SDRAM_Page6*/
  80                         {0x01C00000,SDRAM_DGENERIC},    /*SDRAM_Page7*/
  81                         {0x02000000,SDRAM_DGENERIC},    /*SDRAM_Page8*/
  82                         {0x02400000,SDRAM_DGENERIC},    /*SDRAM_Page9*/
  83                         {0x02800000,SDRAM_DGENERIC},    /*SDRAM_Page10*/
  84                         {0x02C00000,SDRAM_DGENERIC},    /*SDRAM_Page11*/
  85                         {0x03000000,SDRAM_DGENERIC},    /*SDRAM_Page12*/
  86                         {0x20000000,SDRAM_EBIU},        /*For Network */
  87 };
  88
  89 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  90 {
  91         __asm__ __volatile__
  92         ("cli r3;"
  93         "P0 = %0;"
  94         "JUMP (P0);"
  95         :
  96         : "r" (L1_ISRAM)
  97         );
  98
  99         return 0;
 100 }
 101
 102 /* These functions are just used to satisfy the linker */
 103 int cpu_init(void)
 104 {
 105         return 0;
 106 }
 107
 108 int cleanup_before_linux(void)
 109 {
 110         return 0;
 111 }
 112
 113 void icache_enable(void)
 114 {
 115         unsigned int *I0,*I1;
 116         int i;
 117
 118         I0 = (unsigned int *)ICPLB_ADDR0;
 119         I1 = (unsigned int *)ICPLB_DATA0;
 120
 121         for(i=0;i<16;i++){
 122                 *I0++ = icplb_table[i][0];
 123                 *I1++ = icplb_table[i][1];
 124                 }
 125         cli();
 126         SSYNC();
 127         *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
 128         SSYNC();
 129         sti();
 130 }
 131
 132 void icache_disable(void)
 133 {
 134         cli();
 135         SSYNC();
 136         *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
 137         SSYNC();
 138         sti();
 139 }
 140
 141 int icache_status(void)
 142 {
 143         unsigned int value;
 144         value = *(unsigned int *)IMEM_CONTROL;
 145
 146         if( value & (IMC|ENICPLB) )
 147                 return CACHE_ON;
 148         else
 149                 return CACHE_OFF;
 150 }
 151
 152 void dcache_enable(void)
 153 {
 154         unsigned int *I0,*I1;
 155         unsigned int temp;
 156         int i;
 157         I0 = (unsigned int *)DCPLB_ADDR0;
 158         I1 = (unsigned int *)DCPLB_DATA0;
 159
 160         for(i=0;i<16;i++){
 161                 *I0++ = dcplb_table[i][0];
 162                 *I1++ = dcplb_table[i][1];
 163                 }
 164         cli();
 165         temp = *(unsigned int *)DMEM_CONTROL;
 166         SSYNC();
 167         *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
 168         SSYNC();
 169         sti();
 170 }
 171
 172 void dcache_disable(void)
 173 {
 174         cli();
 175         SSYNC();
 176         *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
 177         SSYNC();
 178         sti();
 179 }
 180
 181 int dcache_status(void)
 182 {
 183         unsigned int value;
 184         value = *(unsigned int *)DMEM_CONTROL;
 185         if( value & (ENDCPLB))
 186                 return CACHE_ON;
 187         else
 188                 return CACHE_OFF;
 189 }