2 * U-boot - cpu.c CPU specific functions
4 * Copyright (c) 2005 blackfin.uclinux.org
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/blackfin.h>
31 #include <asm/entry.h>
37 extern unsigned int icplb_table[page_descriptor_table_size][2];
38 extern unsigned int dcplb_table[page_descriptor_table_size][2];
41 #define pr_debug(fmt,arg...) printf(fmt,##arg)
44 __attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
50 int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
52 __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
58 /* These functions are just used to satisfy the linker */
64 int cleanup_before_linux(void)
69 void icache_enable(void)
71 unsigned int *I0, *I1;
74 if ((*pCHIPID >> 28) < 2)
78 /* Before enable icache, disable it first */
80 I0 = (unsigned int *)ICPLB_ADDR0;
81 I1 = (unsigned int *)ICPLB_DATA0;
83 /* make sure the locked ones go in first */
84 for (i = 0; i < page_descriptor_table_size; i++) {
85 if (CPLB_LOCK & icplb_table[i][1]) {
86 pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
87 icplb_table[i][0], icplb_table[i][1]);
88 *I0++ = icplb_table[i][0];
89 *I1++ = icplb_table[i][1];
94 for (i = 0; i < page_descriptor_table_size; i++) {
95 if (!(CPLB_LOCK & icplb_table[i][1])) {
96 pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
97 icplb_table[i][0], icplb_table[i][1]);
98 *I0++ = icplb_table[i][0];
99 *I1++ = icplb_table[i][1];
107 /* Fill the rest with invalid entry */
109 for (; j <= 16; j++) {
110 pr_debug("filling %i with 0", j);
117 __builtin_bfin_ssync();
119 *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
120 __builtin_bfin_ssync();
124 void icache_disable(void)
127 if ((*pCHIPID >> 28) < 2)
131 __builtin_bfin_ssync();
133 *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
134 __builtin_bfin_ssync();
138 int icache_status(void)
141 value = *(unsigned int *)IMEM_CONTROL;
143 if (value & (IMC | ENICPLB))
149 void dcache_enable(void)
151 unsigned int *I0, *I1;
155 /* Before enable dcache, disable it first */
157 I0 = (unsigned int *)DCPLB_ADDR0;
158 I1 = (unsigned int *)DCPLB_DATA0;
160 /* make sure the locked ones go in first */
161 for (i = 0; i < page_descriptor_table_size; i++) {
162 if (CPLB_LOCK & dcplb_table[i][1]) {
163 pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
164 dcplb_table[i][0], dcplb_table[i][1]);
165 *I0++ = dcplb_table[i][0];
166 *I1++ = dcplb_table[i][1];
169 pr_debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
170 dcplb_table[i][0], dcplb_table[i][1]);
174 for (i = 0; i < page_descriptor_table_size; i++) {
175 if (!(CPLB_LOCK & dcplb_table[i][1])) {
176 pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
177 dcplb_table[i][0], dcplb_table[i][1]);
178 *I0++ = dcplb_table[i][0];
179 *I1++ = dcplb_table[i][1];
187 /* Fill the rest with invalid entry */
189 for (; j <= 16; j++) {
190 pr_debug("filling %i with 0", j);
196 temp = *(unsigned int *)DMEM_CONTROL;
197 __builtin_bfin_ssync();
199 *(unsigned int *)DMEM_CONTROL =
200 ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
201 __builtin_bfin_ssync();
205 void dcache_disable(void)
208 unsigned int *I0, *I1;
212 __builtin_bfin_ssync();
214 *(unsigned int *)DMEM_CONTROL &=
215 ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
216 __builtin_bfin_ssync();
219 /* after disable dcache,
220 * clear it so we don't confuse the next application
222 I0 = (unsigned int *)DCPLB_ADDR0;
223 I1 = (unsigned int *)DCPLB_DATA0;
225 for (i = 0; i < 16; i++) {
231 int dcache_status(void)
234 value = *(unsigned int *)DMEM_CONTROL;
235 if (value & (ENDCPLB))