3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
27 /* ----- Ethernet Buffer definitions ----- */
30 unsigned long addr, size;
33 #define RBF_ADDR 0xfffffffc
34 #define RBF_OWNER (1<<0)
35 #define RBF_WRAP (1<<1)
36 #define RBF_BROADCAST (1<<31)
37 #define RBF_MULTICAST (1<<30)
38 #define RBF_UNICAST (1<<29)
39 #define RBF_EXTERNAL (1<<28)
40 #define RBF_UNKOWN (1<<27)
41 #define RBF_SIZE 0x07ff
42 #define RBF_LOCAL4 (1<<26)
43 #define RBF_LOCAL3 (1<<25)
44 #define RBF_LOCAL2 (1<<24)
45 #define RBF_LOCAL1 (1<<23)
47 /* Emac Buffers in last 512KBytes of SDRAM*/
48 /* Be careful, buffer size is limited to 512KBytes !!! */
49 #define RBF_FRAMEMAX 100
50 /*#define RBF_FRAMEMEM 0x200000 */
51 #define RBF_FRAMEMEM 0x21F80000
52 #define RBF_FRAMELEN 0x600
54 #define RBF_FRAMEBTD RBF_FRAMEMEM
55 #define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
58 #ifdef CONFIG_DRIVER_ETHER
60 #if (CONFIG_COMMANDS & CFG_CMD_NET)
62 /* structure to interface the PHY */
63 AT91S_PhyOps AT91S_Dm9161Ops;
64 AT91PS_PhyOps pPhyOps;
68 /*************************** Phy layer functions ************************/
69 /** functions to interface the DAVICOM 10/100Mbps ethernet phy **********/
73 * dm9161_IsPhyConnected
75 * Reads the 2 PHY ID registers
77 * p_mac - pointer to AT91S_EMAC struct
79 * TRUE - if id read successfully
82 static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
84 unsigned short Id1, Id2;
86 at91rm9200_EmacEnableMDIO (p_mac);
87 at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
88 at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
89 at91rm9200_EmacDisableMDIO (p_mac);
91 if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
92 ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
100 * dm9161_GetLinkSpeed
102 * Link parallel detection status of MAC is checked and set in the
103 * MAC configuration registers
105 * p_mac - pointer to MAC
107 * TRUE - if link status set succesfully
108 * FALSE - if link status not set
110 static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
112 unsigned short stat1, stat2;
114 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
117 if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
120 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
123 if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
124 /*set Emac for 100BaseTX and Full Duplex */
125 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
129 if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
130 /*set MII for 10BaseT and Full Duplex */
131 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
132 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
137 if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
138 /*set MII for 100BaseTX and Half Duplex */
139 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
140 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
145 if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
146 /*set MII for 10BaseT and Half Duplex */
147 p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
158 * MAC starts checking its link by using parallel detection and
159 * Autonegotiation and the same is set in the MAC configuration registers
161 * p_mac - pointer to struct AT91S_EMAC
163 * TRUE - if link status set succesfully
164 * FALSE - if link status not set
166 static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
169 unsigned short IntValue;
171 at91rm9200_EmacEnableMDIO (p_mac);
173 if (!dm9161_GetLinkSpeed (p_mac)) {
174 /* Try another time */
175 ret = dm9161_GetLinkSpeed (p_mac);
178 /* Disable PHY Interrupts */
179 at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
180 /* clear FDX, SPD, Link, INTR masks */
181 IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
182 DM9161_LINK_MASK | DM9161_INTR_MASK);
183 at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
184 at91rm9200_EmacDisableMDIO (p_mac);
192 * dm9161_AutoNegotiate
194 * MAC Autonegotiates with the partner status of same is set in the
195 * MAC configuration registers
197 * dev - pointer to struct net_device
199 * TRUE - if link status set successfully
200 * FALSE - if link status not set
202 static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
204 unsigned short value;
205 unsigned short PhyAnar;
206 unsigned short PhyAnalpar;
208 /* Set dm9161 control register */
209 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
211 value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
212 value |= DM9161_ISOLATE; /* Electrically isolate PHY */
213 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
216 /* Set the Auto_negotiation Advertisement Register */
217 /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
218 PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
219 DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
220 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
223 /* Read the Control Register */
224 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
227 value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
228 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
230 /* Restart Auto_negotiation */
231 value |= DM9161_RESTART_AUTONEG;
232 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
235 /*check AutoNegotiate complete */
237 at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
238 if (!(value & DM9161_AUTONEG_COMP))
241 /* Get the AutoNeg Link partner base page */
242 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
245 if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
246 /*set MII for 100BaseTX and Full Duplex */
247 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
251 if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
252 /*set MII for 10BaseT and Full Duplex */
253 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
254 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
264 /*********** EMAC Phy layer Management functions *************************/
267 * at91rm9200_EmacEnableMDIO
269 * Enables the MDIO bit in MAC control register
271 * p_mac - pointer to struct AT91S_EMAC
275 static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
277 /* Mac CTRL reg set for MDIO enable */
278 p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
283 * at91rm9200_EmacDisableMDIO
285 * Disables the MDIO bit in MAC control register
287 * p_mac - pointer to struct AT91S_EMAC
291 static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
293 /* Mac CTRL reg set for MDIO disable */
294 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
300 * at91rm9200_EmacReadPhy
302 * Reads data from the PHY register
304 * dev - pointer to struct net_device
305 * RegisterAddress - unsigned char
306 * pInput - pointer to value read from register
308 * TRUE - if data read successfully
310 static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
311 unsigned char RegisterAddress,
312 unsigned short *pInput)
314 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
315 (AT91C_EMAC_CODE_802_3) | (AT91C_EMAC_RW_R) |
316 (RegisterAddress << 18);
320 *pInput = (unsigned short) p_mac->EMAC_MAN;
328 * at91rm9200_EmacWritePhy
330 * Writes data to the PHY register
332 * dev - pointer to struct net_device
333 * RegisterAddress - unsigned char
334 * pOutput - pointer to value to be written in the register
336 * TRUE - if data read successfully
338 static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
339 unsigned char RegisterAddress,
340 unsigned short *pOutput)
342 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
343 AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
344 (RegisterAddress << 18);
353 * at91rm92000_GetPhyInterface
355 * Initialise the interface functions to the PHY
361 void at91rm92000_GetPhyInterface (void)
363 AT91S_Dm9161Ops.Init = dm9161_InitPhy;
364 AT91S_Dm9161Ops.IsPhyConnected = dm9161_IsPhyConnected;
365 AT91S_Dm9161Ops.GetLinkSpeed = dm9161_GetLinkSpeed;
366 AT91S_Dm9161Ops.AutoNegotiate = dm9161_AutoNegotiate;
368 pPhyOps = (AT91PS_PhyOps) & AT91S_Dm9161Ops;
375 int eth_init (bd_t * bd)
380 p_mac = AT91C_BASE_EMAC;
382 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK; /* PIO Disable Register */
384 *AT91C_PIOB_PDR = AT91C_PB25_EF100 |
385 AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
386 AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
387 AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
389 *AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; /* Select B Register */
391 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
393 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
395 /* Init Ehternet buffers */
396 rbfdt = (rbf_t *) RBF_FRAMEBTD;
397 for (i = 0; i < RBF_FRAMEMAX; i++) {
398 rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
401 rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
404 at91rm92000_GetPhyInterface ();
406 if (!pPhyOps->IsPhyConnected (p_mac))
407 printf ("PHY not connected!!\n\r");
409 /* MII management start from here */
410 if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
411 if (!(ret = pPhyOps->Init (p_mac))) {
412 printf ("MAC: error during MII initialization\n");
416 printf ("No link\n\r");
420 p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
421 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
422 p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
424 p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
425 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
426 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_RMII)
428 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
433 int eth_send (volatile void *packet, int length)
435 while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
436 p_mac->EMAC_TAR = (long) packet;
437 p_mac->EMAC_TCR = length;
438 while (p_mac->EMAC_TCR & 0x7ff);
439 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
447 if (!(rbfp->addr & RBF_OWNER))
450 size = rbfp->size & RBF_SIZE;
451 NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
453 rbfp->addr &= ~RBF_OWNER;
454 if (rbfp->addr & RBF_WRAP)
459 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
467 #endif /* CONFIG_COMMANDS & CFG_CMD_NET */
468 #endif /* CONFIG_DRIVER_ETHER */