2 * Copyright (C) 2005-2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sdram.h>
28 #include <asm/arch/clk.h>
29 #include <asm/arch/memory-map.h>
33 unsigned long sdram_init(const struct sdram_info *info)
35 unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
36 unsigned long sdram_size;
41 tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
42 | HSDRAMC1_BF(NR, info->row_bits - 11)
43 | HSDRAMC1_BF(NB, info->bank_bits - 1)
44 | HSDRAMC1_BF(CAS, info->cas)
45 | HSDRAMC1_BF(TWR, info->twr)
46 | HSDRAMC1_BF(TRC, info->trc)
47 | HSDRAMC1_BF(TRP, info->trp)
48 | HSDRAMC1_BF(TRCD, info->trcd)
49 | HSDRAMC1_BF(TRAS, info->tras)
50 | HSDRAMC1_BF(TXSR, info->txsr));
52 #ifdef CFG_SDRAM_16BIT
53 tmp |= HSDRAMC1_BIT(DBW);
54 sdram_size = 1 << (info->row_bits + info->col_bits
55 + info->bank_bits + 1);
57 sdram_size = 1 << (info->row_bits + info->col_bits
58 + info->bank_bits + 2);
61 hsdramc1_writel(CR, tmp);
64 * Initialization sequence for SDRAM, from the data sheet:
66 * 1. A minimum pause of 200 us is provided to precede any
72 * 2. A Precharge All command is issued to the SDRAM
74 hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
79 * 3. Eight auto-refresh (CBR) cycles are provided
81 hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
83 for (i = 0; i < 8; i++)
87 * 4. A mode register set (MRS) cycle is issued to program
88 * SDRAM parameters, in particular CAS latency and burst
91 * CAS from info struct, burst length 1, serial burst type
93 hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
95 writel(0, sdram + (info->cas << 4));
98 * 5. A Normal Mode command is provided, 3 clocks after tMRD
101 * From the timing diagram, it looks like tMRD is 3
102 * cycles...try a dummy read from the peripheral bus.
105 hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
110 * 6. Write refresh rate into SDRAMC refresh timer count
111 * register (refresh rate = timing between refresh cycles).
113 * 15.6 us is a typical value for a burst of length one
115 bus_hz = get_sdram_clk_rate();
116 hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000);
118 printf("SDRAM: %u MB at address 0x%08lx\n",
119 sdram_size >> 20, info->phys_addr);
121 printf("Testing SDRAM...");
122 for (i = 0; i < sdram_size / 4; i++)
125 for (i = 0; i < sdram_size / 4; i++) {
128 printf("FAILED at address 0x%08lx\n",
129 info->phys_addr + i * 4);
130 printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
140 #endif /* CFG_HSDRAMC */