5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Syed Moahmmed Khasim <khasim@ti.com>
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 * Alex Zuepke <azu@sysgo.de>
14 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/proc-armv/ptrace.h>
40 /* enable IRQ interrupts */
41 void enable_interrupts(void)
44 __asm__ __volatile__("mrs %0, cpsr\n"
45 "bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
50 * disable IRQ/FIQ interrupts
51 * returns true if interrupts had been enabled before we disabled them
53 int disable_interrupts(void)
55 unsigned long old, temp;
56 __asm__ __volatile__("mrs %0, cpsr\n"
58 "msr cpsr_c, %1":"=r"(old), "=r"(temp)
60 return (old & 0x80) == 0;
63 void enable_interrupts(void)
67 int disable_interrupts(void)
75 panic("Resetting CPU ...\n");
79 void show_regs(struct pt_regs *regs)
82 const char *processor_modes[] = {
83 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
84 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
85 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
86 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
87 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
88 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
89 "UK8_32", "UK9_32", "UK10_32", "UND_32",
90 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
93 flags = condition_codes(regs);
95 printf("pc : [<%08lx>] lr : [<%08lx>]\n"
96 "sp : %08lx ip : %08lx fp : %08lx\n",
97 instruction_pointer(regs),
98 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
99 printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
100 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
101 printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
102 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
103 printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
104 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
105 printf("Flags: %c%c%c%c",
106 flags & CC_N_BIT ? 'N' : 'n',
107 flags & CC_Z_BIT ? 'Z' : 'z',
108 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
109 printf(" IRQs %s FIQs %s Mode %s%s\n",
110 interrupts_enabled(regs) ? "on" : "off",
111 fast_interrupts_enabled(regs) ? "on" : "off",
112 processor_modes[processor_mode(regs)],
113 thumb_mode(regs) ? " (T)" : "");
116 void do_undefined_instruction(struct pt_regs *pt_regs)
118 printf("undefined instruction\n");
123 void do_software_interrupt(struct pt_regs *pt_regs)
125 printf("software interrupt\n");
130 void do_prefetch_abort(struct pt_regs *pt_regs)
132 printf("prefetch abort\n");
137 void do_data_abort(struct pt_regs *pt_regs)
139 printf("data abort\n");
144 void do_not_used(struct pt_regs *pt_regs)
146 printf("not used\n");
151 void do_fiq(struct pt_regs *pt_regs)
153 printf("fast interrupt request\n");
158 void do_irq(struct pt_regs *pt_regs)
160 printf("interrupt request\n");
166 static ulong timestamp;
167 static ulong lastinc;
168 static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
171 * Nothing really to do with interrupts, just starts up a counter.
172 * We run the counter with 13MHz, divided by 8, resulting in timer
173 * frequency of 1.625MHz. With 32bit counter register, counter
174 * overflows in ~44min
177 /* 13MHz / 8 = 1.625MHz */
178 #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
179 #define TIMER_LOAD_VAL 0xffffffff
181 int interrupt_init(void)
183 /* start the counter ticking up, reload value on overflow */
184 writel(TIMER_LOAD_VAL, &timer_base->tldr);
186 writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
189 reset_timer_masked(); /* init the timestamp and lastinc value */
195 * timer without interrupts
197 void reset_timer(void)
199 reset_timer_masked();
202 ulong get_timer(ulong base)
204 return get_timer_masked() - base;
207 void set_timer(ulong t)
212 /* delay x useconds */
213 void udelay(unsigned long usec)
215 long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
216 unsigned long now, last = readl(&timer_base->tcrr);
219 now = readl(&timer_base->tcrr);
220 if (last > now) /* count up timer overflow */
221 tmo -= TIMER_LOAD_VAL - last + now;
228 void reset_timer_masked(void)
230 /* reset time, capture current incrementer value time */
231 lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
232 timestamp = 0; /* start "advancing" time stamp from 0 */
235 ulong get_timer_masked(void)
237 /* current tick value */
238 ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
240 if (now >= lastinc) /* normal mode (non roll) */
241 /* move stamp fordward with absoulte diff ticks */
242 timestamp += (now - lastinc);
243 else /* we have rollover of incrementer */
244 timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
251 * This function is derived from PowerPC code (read timebase as long long).
252 * On ARM it just returns the timer value.
254 unsigned long long get_ticks(void)
260 * This function is derived from PowerPC code (timebase clock frequency).
261 * On ARM it returns the number of timer ticks per second.
263 ulong get_tbclk(void)
265 return CONFIG_SYS_HZ;