2 * (C) Copyright 2008 Texas Insturments
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
9 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/sys_proto.h>
37 #include <asm/system.h>
40 DECLARE_GLOBAL_DATA_PTR;
44 void l2cache_disable(void);
47 static void cache_flush(void);
49 static void cp_delay(void)
51 /* Many OMAP regs need at least 2 nops */
59 * setup up stacks if necessary
63 _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
64 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
69 int cleanup_before_linux(void)
74 * this function is called just before we call linux
75 * it prepares the processor for linux
77 * we turn off caches etc ...
81 /* turn off I/D-cache */
85 /* invalidate I-cache */
89 /* turn off L2 cache */
91 /* invalidate L2 cache also */
92 v7_flush_dcache_all(get_device_type());
95 /* mem barrier to sync up things */
96 asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
105 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
107 disable_interrupts();
114 void icache_enable(void)
118 reg = get_cr(); /* get control reg. */
123 void icache_disable(void)
132 void dcache_disable (void)
138 set_cr (reg & ~CR_C);
141 void l2cache_enable()
144 volatile unsigned int j;
146 /* ES2 onwards we can disable/enable L2 ourselves */
147 if (get_cpu_rev() == CPU_3430_ES2) {
148 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
149 __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
150 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
152 /* Save r0, r12 and restore them after usage */
153 __asm__ __volatile__("mov %0, r12":"=r"(j));
154 __asm__ __volatile__("mov %0, r0":"=r"(i));
157 * GP Device ROM code API usage here
158 * r12 = AUXCR Write function and r0 value
160 __asm__ __volatile__("mov r12, #0x3");
161 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
162 __asm__ __volatile__("orr r0, r0, #0x2");
163 /* SMI instruction to call ROM Code API */
164 __asm__ __volatile__(".word 0xE1600070");
165 __asm__ __volatile__("mov r0, %0":"=r"(i));
166 __asm__ __volatile__("mov r12, %0":"=r"(j));
171 void l2cache_disable()
174 volatile unsigned int j;
176 /* ES2 onwards we can disable/enable L2 ourselves */
177 if (get_cpu_rev() == CPU_3430_ES2) {
178 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
179 __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
180 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
182 /* Save r0, r12 and restore them after usage */
183 __asm__ __volatile__("mov %0, r12":"=r"(j));
184 __asm__ __volatile__("mov %0, r0":"=r"(i));
187 * GP Device ROM code API usage here
188 * r12 = AUXCR Write function and r0 value
190 __asm__ __volatile__("mov r12, #0x3");
191 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
192 __asm__ __volatile__("bic r0, r0, #0x2");
193 /* SMI instruction to call ROM Code API */
194 __asm__ __volatile__(".word 0xE1600070");
195 __asm__ __volatile__("mov r0, %0":"=r"(i));
196 __asm__ __volatile__("mov r12, %0":"=r"(j));
200 int icache_status(void)
202 return (get_cr() & CR_I) != 0;
205 static void cache_flush(void)
207 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));