3 * Texas Instruments <www.ti.com>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
13 * (C) Copyright 2002-2004
14 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
17 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 #include <asm/proc-armv/ptrace.h>
42 #define TIMER_LOAD_VAL 0xffffffff
43 extern void reset_cpu(ulong addr);
46 /* enable IRQ interrupts */
47 void enable_interrupts (void)
50 __asm__ __volatile__("mrs %0, cpsr\n"
60 * disable IRQ/FIQ interrupts
61 * returns true if interrupts had been enabled before we disabled them
63 int disable_interrupts (void)
65 unsigned long old,temp;
66 __asm__ __volatile__("mrs %0, cpsr\n"
69 : "=r" (old), "=r" (temp)
72 return (old & 0x80) == 0;
75 void enable_interrupts (void)
79 int disable_interrupts (void)
88 panic ("Resetting CPU ...\n");
92 void show_regs (struct pt_regs *regs)
95 const char *processor_modes[] = {
96 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
97 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
98 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
99 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
100 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
101 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
102 "UK8_32", "UK9_32", "UK10_32", "UND_32",
103 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
106 flags = condition_codes (regs);
108 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
109 "sp : %08lx ip : %08lx fp : %08lx\n",
110 instruction_pointer (regs),
111 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
112 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
113 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
114 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
115 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
116 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
117 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
118 printf ("Flags: %c%c%c%c",
119 flags & CC_N_BIT ? 'N' : 'n',
120 flags & CC_Z_BIT ? 'Z' : 'z',
121 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
122 printf (" IRQs %s FIQs %s Mode %s%s\n",
123 interrupts_enabled (regs) ? "on" : "off",
124 fast_interrupts_enabled (regs) ? "on" : "off",
125 processor_modes[processor_mode (regs)],
126 thumb_mode (regs) ? " (T)" : "");
129 void do_undefined_instruction (struct pt_regs *pt_regs)
131 printf ("undefined instruction\n");
136 void do_software_interrupt (struct pt_regs *pt_regs)
138 printf ("software interrupt\n");
143 void do_prefetch_abort (struct pt_regs *pt_regs)
145 printf ("prefetch abort\n");
150 void do_data_abort (struct pt_regs *pt_regs)
152 printf ("data abort\n");
157 void do_not_used (struct pt_regs *pt_regs)
159 printf ("not used\n");
164 void do_fiq (struct pt_regs *pt_regs)
166 printf ("fast interrupt request\n");
171 void do_irq (struct pt_regs *pt_regs)
173 printf ("interrupt request\n");
178 #ifdef CONFIG_INTEGRATOR
179 /* Timer functionality supplied by Integrator board (AP or CP) */
182 static ulong timestamp;
183 static ulong lastdec;
185 /* nothing really to do with interrupts, just starts up a counter. */
186 int interrupt_init (void)
188 /* init the timestamp and lastdec value */
189 reset_timer_masked();
195 * timer without interrupts
198 void reset_timer (void)
200 reset_timer_masked ();
203 ulong get_timer (ulong base)
205 return get_timer_masked () - base;
208 void set_timer (ulong t)
213 /* delay x useconds AND perserve advance timstamp value */
214 void udelay(unsigned long usec)
219 void reset_timer_masked (void)
222 lastdec = READ_TIMER; /* capure current decrementer value time */
223 timestamp = 0; /* start "advancing" time stamp from 0 */
226 ulong get_timer_raw (void)
228 ulong now = READ_TIMER; /* current tick value */
230 if (lastdec >= now) { /* normal mode (non roll) */
232 timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
233 } else { /* we have overflow of the count down timer */
234 /* nts = ts + ld + (TLV - now)
235 * ts=old stamp, ld=time that passed before passing through -1
236 * (TLV-now) amount of time after passing though -1
237 * nts = new "advancing time stamp"...it could also roll and cause problems.
239 timestamp += lastdec + TIMER_LOAD_VAL - now;
246 ulong get_timer_masked (void)
248 return get_timer_raw() / TIMER_LOAD_VAL;
251 /* waits specified delay value and resets timestamp */
252 void udelay_masked (unsigned long usec)
256 if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
257 tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
258 tmo *= CFG_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */
259 tmo /= 1000; /* finish normalize. */
260 }else{ /* else small number, don't kill it prior to HZ multiply */
261 tmo = usec * CFG_HZ_CLOCK;
265 reset_timer_masked (); /* set "advancing" timestamp to 0, set lastdec vaule */
267 while (get_timer_raw () < tmo) /* wait for time stamp to overtake tick number.*/
272 * This function is derived from PowerPC code (read timebase as long long).
273 * On ARM it just returns the timer value.
275 unsigned long long get_ticks(void)
281 * This function is derived from PowerPC code (timebase clock frequency).
282 * On ARM it returns the number of timer ticks per second.
284 ulong get_tbclk (void)
292 #endif /* CONFIG_INTEGRATOR */