2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #if defined(CONFIG_OMAP1610)
38 #include <./configs/omap1510.h>
42 *************************************************************************
44 * Jump vector table as in table 3.1 in [1]
46 *************************************************************************
53 ldr pc, _undefined_instruction
54 ldr pc, _software_interrupt
55 ldr pc, _prefetch_abort
61 _undefined_instruction:
62 .word undefined_instruction
64 .word software_interrupt
76 .balignl 16,0xdeadbeef
80 *************************************************************************
82 * Startup Code (reset vector)
84 * do important init only if we don't start from memory!
85 * setup Memory and board specific bits prior to relocation.
86 * relocate armboot to ram
89 *************************************************************************
100 * These are defined in the board-specific linker script.
110 #ifdef CONFIG_USE_IRQ
111 /* IRQ stack memory (calculated at run-time) */
112 .globl IRQ_STACK_START
116 /* IRQ stack memory (calculated at run-time) */
117 .globl FIQ_STACK_START
124 * the actual reset code
129 * set the cpu to SVC32 mode
137 * we do sys-critical inits only at reboot,
138 * not when booting from ram!
140 #ifdef CONFIG_INIT_CRITICAL
144 relocate: /* relocate U-Boot to RAM */
145 adr r0, _start /* r0 <- current position of code */
146 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
147 cmp r0, r1 /* don't reloc during debug */
150 ldr r2, _armboot_start
152 sub r2, r3, r2 /* r2 <- size of armboot */
153 add r2, r0, r2 /* r2 <- source end address */
156 ldmia r0!, {r3-r10} /* copy from source address [r0] */
157 stmia r1!, {r3-r10} /* copy to target address [r1] */
158 cmp r0, r2 /* until source end addreee [r2] */
161 /* Set up the stack */
163 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
164 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
165 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
166 #ifdef CONFIG_USE_IRQ
167 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
169 sub sp, r0, #12 /* leave 3 words for abort-stack */
172 ldr r0, _bss_start /* find start of bss segment */
173 add r0, r0, #4 /* start at first byte of bss */
174 ldr r1, _bss_end /* stop here */
175 mov r2, #0x00000000 /* clear */
177 clbss_l:str r2, [r0] /* clear loop... */
182 ldr pc, _start_armboot
189 *************************************************************************
191 * CPU_init_critical registers
193 * setup important registers
194 * setup memory timing
196 *************************************************************************
202 * flush v4 I/D caches
205 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
206 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
209 * disable MMU stuff and caches
211 mrc p15, 0, r0, c1, c0, 0
212 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
213 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
214 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
215 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
216 mcr p15, 0, r0, c1, c0, 0
219 * Go setup Memory and board specific bits prior to relocation.
221 mov ip, lr /* perserve link reg across call */
222 bl platformsetup /* go setup pll,mux,memory */
223 mov lr, ip /* restore link */
224 mov pc, lr /* back to my caller */
226 *************************************************************************
230 *************************************************************************
236 #define S_FRAME_SIZE 72
258 #define MODE_SVC 0x13
262 * use bad_save_user_regs for abort/prefetch/undef/swi ...
263 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
266 .macro bad_save_user_regs
267 @ carve out a frame on current user stack
268 sub sp, sp, #S_FRAME_SIZE
269 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
271 ldr r2, _armboot_start
272 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
273 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
274 @ get values for "aborted" pc and cpsr (into parm regs)
276 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
279 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
280 mov r0, sp @ save current stack into r0 (param register)
283 .macro irq_save_user_regs
284 sub sp, sp, #S_FRAME_SIZE
285 stmia sp, {r0 - r12} @ Calling r0-r12
286 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
288 stmdb r8, {sp, lr}^ @ Calling SP, LR
289 str lr, [r8, #0] @ Save calling PC
291 str r6, [r8, #4] @ Save CPSR
292 str r0, [r8, #8] @ Save OLD_R0
296 .macro irq_restore_user_regs
297 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
299 ldr lr, [sp, #S_PC] @ Get PC
300 add sp, sp, #S_FRAME_SIZE
301 subs pc, lr, #4 @ return & move spsr_svc into cpsr
305 ldr r13, _armboot_start @ setup our mode stack
306 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
307 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
309 str lr, [r13] @ save caller lr in position 0 of saved stack
310 mrs lr, spsr @ get the spsr
311 str lr, [r13, #4] @ save spsr in position 1 of saved stack
312 mov r13, #MODE_SVC @ prepare SVC-Mode
314 msr spsr, r13 @ switch modes, make sure moves will execute
315 mov lr, pc @ capture return pc
316 movs pc, lr @ jump to next instruction & switch modes.
319 .macro get_irq_stack @ setup IRQ stack
320 ldr sp, IRQ_STACK_START
323 .macro get_fiq_stack @ setup FIQ stack
324 ldr sp, FIQ_STACK_START
331 undefined_instruction:
334 bl do_undefined_instruction
340 bl do_software_interrupt
360 #ifdef CONFIG_USE_IRQ
367 irq_restore_user_regs
372 /* someone ought to write a more effiction fiq_save_user_regs */
375 irq_restore_user_regs
396 ldr r1, rstctl1 /* get clkm1 reset ctl */
398 strh r3, [r1] /* clear it */
400 strh r3, [r1] /* force dsp+arm reset */