2 * Low-level board setup code for TI DaVinci SoC based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Partially based on TI sources, original copyrights follow:
10 * Board specific setup info
13 * Texas Instruments, <www.ti.com>
14 * Kshitij Gupta <Kshitij@ti.com>
16 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
18 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
19 * See file CREDITS for list of people who contributed to this
22 * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
23 * See file CREDITS for list of people who contributed to this
26 * Modified for DV-EVM board by Swaminathan S, Nov 2005
27 * See file CREDITS for list of people who contributed to this
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
51 /*-------------------------------------------------------*
52 * Mask all IRQs by setting all bits in the EINT default *
53 *-------------------------------------------------------*/
60 /*------------------------------------------------------*
61 * Put the GEM in reset *
62 *------------------------------------------------------*/
64 /* Put the GEM in reset */
65 ldr r8, PSC_GEM_FLAG_CLEAR
71 /* Enable the Power Domain Transition Command */
77 /* Check for Transition Complete(PTSTAT) */
82 bne checkStatClkStopGem
84 /* Check for GEM Reset Completion */
89 bne checkGemStatClkStop
91 /* Do this for enabling a WDT initiated reset this is a workaround
92 for a chip bug. Not required under normal situations */
97 /*------------------------------------------------------*
98 * Enable L1 & L2 Memories in Fast mode *
99 *------------------------------------------------------*/
105 ldr r10, MMARG_BRF0_VAL
112 /*------------------------------------------------------*
113 * DDR2 PLL Initialization *
114 *------------------------------------------------------*/
116 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
119 ldr r7, PLL_CLKSRC_MASK
126 /* Select the PLLEN source */
127 ldr r7, PLL_ENSRC_MASK
132 ldr r7, PLL_BYPASS_MASK
136 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
143 ldr r7, PLL_RESET_MASK
147 /* Power up the PLL */
148 ldr r7, PLL_PWRUP_MASK
152 /* Enable the PLL from Disable Mode */
153 ldr r7, PLL_DISABLE_ENABLE_MASK
157 /* Program the PLL Multiplier */
159 mov r2, $0x17 /* 162 MHz */
162 /* Program the PLL2 Divisor Value */
167 /* Program the PLL2 Divisor Value */
169 mov r4, $0x0b /* 54 MHz */
173 ldr r8, PLL2_DIV_MASK
182 /* Program the GOSET bit to take new divider values */
196 ldr r8, PLL2_DIV_MASK
205 /* Program the GOSET bit to take new divider values */
218 /* Wait for PLL to Reset Properly */
224 /* Bring PLL out of Reset */
230 /* Wait for PLL to Lock */
231 ldr r10, PLL_LOCK_COUNT
242 /*------------------------------------------------------*
243 * Issue Soft Reset to DDR Module *
244 *------------------------------------------------------*/
246 /* Shut down the DDR2 LPSC Module */
247 ldr r8, PSC_FLAG_CLEAR
254 /* Enable the Power Domain Transition Command */
260 /* Check for Transition Complete(PTSTAT) */
267 /* Check for DDR2 Controller Enable Completion */
273 bne checkDDRStatClkStop
275 /*------------------------------------------------------*
276 * Program DDR2 MMRs for 162MHz Setting *
277 *------------------------------------------------------*/
279 /* Program PHY Control Register */
284 /* Program SDRAM Bank Config Register */
289 /* Program SDRAM TIM-0 Config Register */
291 ldr r7, SDTIM0_VAL_162MHz
294 /* Program SDRAM TIM-1 Config Register */
296 ldr r7, SDTIM1_VAL_162MHz
299 /* Program the SDRAM Bank Config Control Register */
306 /* Program SDRAM SDREF Config Register */
311 /*------------------------------------------------------*
312 * Issue Soft Reset to DDR Module *
313 *------------------------------------------------------*/
315 /* Issue a Dummy DDR2 read/write */
316 ldr r8, DDR2_START_ADDR
321 /* Shut down the DDR2 LPSC Module */
322 ldr r8, PSC_FLAG_CLEAR
329 /* Enable the Power Domain Transition Command */
335 /* Check for Transition Complete(PTSTAT) */
340 bne checkStatClkStop2
342 /* Check for DDR2 Controller Enable Completion */
343 checkDDRStatClkStop2:
348 bne checkDDRStatClkStop2
350 /*------------------------------------------------------*
351 * Turn DDR2 Controller Clocks On *
352 *------------------------------------------------------*/
354 /* Enable the DDR2 LPSC Module */
360 /* Enable the Power Domain Transition Command */
366 /* Check for Transition Complete(PTSTAT) */
373 /* Check for DDR2 Controller Enable Completion */
379 bne checkDDRStatClkEn2
381 /* DDR Writes and Reads */
386 /*------------------------------------------------------*
387 * System PLL Initialization *
388 *------------------------------------------------------*/
390 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
393 ldr r7, PLL_CLKSRC_MASK
400 /* Select the PLLEN source */
401 ldr r7, PLL_ENSRC_MASK
406 ldr r7, PLL_BYPASS_MASK
410 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
418 ldr r7, PLL_RESET_MASK
422 /* Disable the PLL */
426 /* Power up the PLL */
427 ldr r7, PLL_PWRUP_MASK
431 /* Enable the PLL from Disable Mode */
432 ldr r7, PLL_DISABLE_ENABLE_MASK
436 /* Program the PLL Multiplier */
438 mov r3, $0x15 /* For 594MHz */
441 /* Wait for PLL to Reset Properly */
448 /* Bring PLL out of Reset */
453 /* Wait for PLL to Lock */
454 ldr r10, PLL_LOCK_COUNT
469 /*------------------------------------------------------*
470 * AEMIF configuration for NOR Flash (double check) *
471 *------------------------------------------------------*/
500 /*--------------------------------------*
501 * VTP manual Calibration *
502 *--------------------------------------*/
511 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
512 ldr r10, VTP_LOCK_COUNT
533 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
534 ldr r10, VTP_LOCK_COUNT
549 * Call board-specific lowlevel init.
550 * That MUST be present and THAT returns
551 * back to arch calling code with "mov pc, lr."
558 .word 0x01c40000 /* Device Configuration Registers */
560 .word 0x01c40004 /* Device Configuration Registers */
602 /* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
616 #elif defined DDR_8BANKS
619 #error "Unknown DDR configuration!!!"
630 .word 0x200000f0 /* VTP IO Control register */
632 .word 0x01c42030 /* DDR VPTR MMR */
652 /* GEM Power Up & LPSC Control Register */
658 /* For WDT reset chip bug */
663 .word 0xfffffeff /* Mask the Clock Mode bit */
665 .word 0xffffffdf /* Select the PLLEN source */
667 .word 0xfffffffe /* Put the PLL in BYPASS */
669 .word 0xfffffff7 /* Put the PLL in Reset Mode */
671 .word 0xfffffffd /* PLL Power up Mask Bit */
672 PLL_DISABLE_ENABLE_MASK:
673 .word 0xffffffef /* Enable the PLL from Disable */
677 /* PLL1-SYSTEM PLL MMRs */
683 /* PLL2-SYSTEM PLL MMRs */
700 .word 0x01c42010 /* BRF margin mode 0 (R/W)*/