3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <arm926ejs.h>
35 #include <asm/system.h>
38 DECLARE_GLOBAL_DATA_PTR;
41 static void cp_delay (void)
45 /* copro seems to need some delay between reading and writing */
46 for (i = 0; i < 100; i++);
52 * setup up stacks if necessary
55 IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
56 FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
61 int cleanup_before_linux (void)
64 * this function is called just before we call linux
65 * it prepares the processor for linux
67 * we turn off caches etc ...
72 disable_interrupts ();
74 /* turn off I/D-cache */
75 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
77 asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
81 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
86 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
88 disable_interrupts ();
94 /* cache_bit must be either CR_I or CR_C */
95 static void cache_enable(uint32_t cache_bit)
99 reg = get_cr(); /* get control reg. */
101 set_cr(reg | cache_bit);
104 /* cache_bit must be either CR_I or CR_C */
105 static void cache_disable(uint32_t cache_bit)
111 set_cr(reg & ~cache_bit);
114 void icache_enable(void)
119 void icache_disable(void)
124 int icache_status(void)
126 return (get_cr() & CR_I) != 0;
129 void dcache_enable(void)
134 void dcache_disable(void)
139 int dcache_status(void)
141 return (get_cr() & CR_C) != 0;